公开(公告)号：US20180315698A1

公开(公告)日：2018-11-01

申请号：US16029030

申请日：2018-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： JinGyu Kim ,  Taehun Kim ,  JiSun Hong ,  Byungmoon Bae ,  Se-Ho You

IPC: H01L23/498 ,  H01L23/60

CPC classification number: H01L23/49838 ,  H01L23/293 ,  H01L23/49816 ,  H01L23/562 ,  H01L23/60 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16237 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/3511

Abstract: A package substrate includes a substrate including a circuit region, a dummy region surrounding the circuit region, and a lower circuit pattern at the dummy region, the circuit region including unit regions arranged in a matrix shape, and solders on the lower circuit pattern, at least one of the solders electrically connected to the lower circuit pattern.

公开(公告)号：US10256181B2

公开(公告)日：2019-04-09

申请号：US16029030

申请日：2018-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： JinGyu Kim ,  Taehun Kim ,  JiSun Hong ,  Byungmoon Bae ,  Se-Ho You

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/60 ,  H01L23/29

Abstract: A package substrate includes a substrate including a circuit region, a dummy region surrounding the circuit region, and a lower circuit pattern at the dummy region, the circuit region including unit regions arranged in a matrix shape, and solders on the lower circuit pattern, at least one of the solders electrically connected to the lower circuit pattern.

公开(公告)号：US09112062B2

公开(公告)日：2015-08-18

申请号：US13974254

申请日：2013-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： JiSun Hong ,  Hyunki Kim ,  JongBo Shim ,  SeokWon Lee ,  Kyoungsei Choi

IPC: H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L24/97 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/00

Abstract: A semiconductor device includes a first semiconductor package including a first mold part, a second semiconductor package including a second mold part, a connecting pattern configured to electrically connect the first and second semiconductor packages to each other, and a molding pattern between the first and second semiconductor packages. The molding pattern extends to cover at least a portion of a sidewall of only the second semiconductor package.

Abstract translation: 一种半导体器件包括：第一半导体封装，包括第一模具部件，包括第二模具部件的第二半导体封装，被配置为使第一和第二半导体封装彼此电连接的连接图案;以及第一和第二半导体封装之间的模制图案 半导体封装。 模制图案延伸以覆盖仅第二半导体封装的侧壁的至少一部分。

公开(公告)号：US10032706B2

公开(公告)日：2018-07-24

申请号：US15236868

申请日：2016-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： JinGyu Kim ,  Taehun Kim ,  JiSun Hong ,  Byungmoon Bae ,  Se-Ho You

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/60 ,  H01L23/29

CPC classification number: H01L23/49838 ,  H01L23/293 ,  H01L23/49816 ,  H01L23/562 ,  H01L23/60 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16237 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/3511

Abstract: A package substrate includes a substrate including a circuit region, a dummy region surrounding the circuit region, and a lower circuit pattern at the dummy region, the circuit region including unit regions arranged in a matrix shape, and solders on the lower circuit pattern, at least one of the solders electrically connected to the lower circuit pattern.