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    PROCESSOR, SYSTEM, AND METHOD FOR DYNAMIC CACHE ALLOCATION
    1.
    发明公开
    PROCESSOR, SYSTEM, AND METHOD FOR DYNAMIC CACHE ALLOCATION 审中-公开

    公开(公告)号：US20240311302A1

    公开(公告)日：2024-09-19

    申请号：US18589852

    申请日：2024-02-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jin Jung ,  Daehoon Kim ,  Hwanjun Lee ,  Jonggeon Lee ,  Jinin So

    IPC: G06F12/0811 ,  G06F12/084

    CPC classification number: G06F12/0811 ,  G06F12/084

    Abstract: A processor includes a processing core configured to process each of a plurality of requests by accessing a corresponding one of a first memory and a second memory, a latency monitor configured to generate first latency information and second latency information, the first latency information comprising a first access latency to the first memory, and the second latency information comprising a second access latency to the second memory, a plurality of cache ways divided into a first partition and a second partition, and a decision engine configured to allocate each of the plurality of cache ways to one of the first partition and the second partition, based on the first latency information and the second latency information.

    DISPLAY APPARATUS
    3.
    发明申请
    DISPLAY APPARATUS 审中-公开

    公开(公告)号：US20200064677A1

    公开(公告)日：2020-02-27

    申请号：US16549746

    申请日：2019-08-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang Ki YOON ,  Yoon Ah Kim ,  Huu Lam Vuong Nguyen ,  Kwang Sung Hwang ,  Jin Jung

    IPC: G02F1/1333 ,  G06F1/16 ,  H01R13/62

    Abstract: A display apparatus includes a frame; a display module including at least one substrate on which a plurality of light emitting elements is mounted, and a bracket to which the at least one substrate is attached; and a magnetic coupling device including a holder fastened to the frame and configured to support the display module, and a magnet received in the holder and configured to apply a magnetic attraction force to pull the display module, wherein the holder may include an adjustment device configured to adjust a position of the display module with respect to the frame while the display module is supported by the frame.

    Memory modules and memory systems having the same
    4.
    发明授权
    Memory modules and memory systems having the same 有权

    公开(公告)号：US11531496B2

    公开(公告)日：2022-12-20

    申请号：US17154030

    申请日：2021-01-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yongsuk Kwon ,  Jinin So ,  Jonggeon Lee ,  Kyungsoo Kim ,  Jin Jung ,  Jeonghyeon Cho

    IPC: G06F3/06 ,  G06F1/08

    Abstract: Memory modules and memory systems having the same are provided. A memory module may include command/address terminals, data terminals, at least one monitoring terminal, a buffer, and a plurality of semiconductor memory devices. The buffer may be configured to receive and buffer data applied through the data terminals and a command/address applied through the command/address terminals to generate buffered write data and a buffered command/address. The buffer may be configured to buffer the buffered write data and the buffered command/address to generate module data and a module command/address, and store and then transmit at least one portion of the buffered write data as monitoring data through the at least one monitoring terminal. The plurality of semiconductor memory devices may be configured to receive and store the module data in response to the module command/address.

    MEMORY MODULES AND MEMORY SYSTEMS HAVING THE SAME
    5.
    发明申请
    MEMORY MODULES AND MEMORY SYSTEMS HAVING THE SAME 有权

    公开(公告)号：US20220027090A1

    公开(公告)日：2022-01-27

    申请号：US17154030

    申请日：2021-01-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yongsuk Kwon ,  Jinin So ,  Jonggeon Lee ,  Kyungsoo Kim ,  Jin Jung ,  Jeonghyeon Cho

    IPC: G06F3/06 ,  G06F1/08

    Abstract: Memory modules and memory systems having the same are provided. A memory module may include command/address terminals, data terminals, at least one monitoring terminal, a buffer, and a plurality of semiconductor memory devices. The buffer may be configured to receive and buffer data applied through the data terminals and a command/address applied through the command/address terminals to generate buffered write data and a buffered command/address. The buffer may be configured to buffer the buffered write data and the buffered command/address to generate module data and a module command/address, and store and then transmit at least one portion of the buffered write data as monitoring data through the at least one monitoring terminal. The plurality of semiconductor memory devices may be configured to receive and store the module data in response to the module command/address.

    MEMORY SYSTEMS AND METHODS FOR OPERATING MEMORY SYSTEMS
    7.
    发明申请
    MEMORY SYSTEMS AND METHODS FOR OPERATING MEMORY SYSTEMS 有权

    公开(公告)号：US20250077433A1

    公开(公告)日：2025-03-06

    申请号：US18604783

    申请日：2024-03-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Daehoon Kim ,  Hyungwon Park ,  Jin Jung ,  Minho Kim ,  Jin In So ,  Jong-Geon Lee ,  Hwanjun Lee ,  Minwoo Jang ,  Yeaji Jung

    IPC: G06F12/0862

    Abstract: Memory systems and methods for operating the same. A memory system comprises a first memory, a second memory having an operating speed different from that of the first memory, a storage unit configured to store an instruction, a prefetcher configured to update prefetcher data in response to occurrence of cache hits and a processor configured to execute the instruction stored in the storage unit. When the instruction is executed, the processor is configured to generate prefetcher friendly data by filtering the prefetcher data, set a prefetcher friendly bit in a first pointer area corresponding to the first memory and a second pointer area corresponding to the second memory based on the prefetcher friendly data, and determine whether data of the first pointer area and the second pointer area are migrated, in consideration of a reference bit and the prefetcher friendly bit of the first and second pointer areas.

    COMPUTING SYSTEMS HAVING CONGESTION MONITORS THEREIN AND METHODS OF CONTROLLING OPERATION OF SAME
    8.
    发明公开
    COMPUTING SYSTEMS HAVING CONGESTION MONITORS THEREIN AND METHODS OF CONTROLLING OPERATION OF SAME 审中-公开

    公开(公告)号：US20240281402A1

    公开(公告)日：2024-08-22

    申请号：US18460954

    申请日：2023-09-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jin Jung ,  Younghyun Lee ,  Yongsuk Kwon ,  Kyungsoo Kim ,  Jinin So

    IPC: G06F13/42

    CPC classification number: G06F13/4282 ,  G06F2213/0002

    Abstract: A computing system includes an interconnect device, a plurality of memory devices electrically coupled to communicate with the interconnect device, a plurality of host devices electrically coupled to communicate with the interconnect device and configured to generate requests for access to the plurality of memory devices via the interconnect device, and a plurality of congestion monitors. These congestion monitors are configured to generate congestion information by monitoring a congestion degree of signal transfers with respect to at least one of the plurality of memory devices and the interconnect device in real time. The computing system is also configured to control at least one of: a memory region allocation of the plurality of host devices to the plurality of memory devices, and a signal transfer path inside the interconnect device, based on the congestion information.

    Memory modules and methods of operating same
    9.
    发明授权
    Memory modules and methods of operating same 有权

    公开(公告)号：US11531618B2

    公开(公告)日：2022-12-20

    申请号：US17157323

    申请日：2021-01-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyungsoo Kim ,  Jinin So ,  Jong-Geon Lee ,  Yongsuk Kwon ,  Jin Jung ,  Jeonghyeon Cho

    IPC: G06F12/0804 ,  G06F11/20 ,  G11C11/4093 ,  G11C11/4096 ,  H04N21/426

    Abstract: A memory module includes a first memory device, a second memory device, and a processing buffer circuit that is connected to the first memory device and the second memory device (independently of each other) and a host. A processing buffer circuit is provided, which includes a processing circuit and a buffer. The processing circuit processes at least one of data received from the host, data stored in the first memory device, or data stored in the second memory device based on a processing command received from the host. The buffer is configured to store data processed by the processing circuit. The processing buffer circuit is configured to communicate with the host in compliance with a DDR SDRAM standard.

    MEMORY MODULES AND METHODS OF OPERATING SAME
    10.
    发明申请
    MEMORY MODULES AND METHODS OF OPERATING SAME 有权

    公开(公告)号：US20210390049A1

    公开(公告)日：2021-12-16

    申请号：US17157323

    申请日：2021-01-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyungsoo Kim ,  Jinin So ,  Jong-Geon Lee ,  Yongsuk Kwon ,  Jin Jung ,  Jeonghyeon Cho

    IPC: G06F12/0804 ,  G06F11/20 ,  G11C11/4096 ,  G11C11/4093

    Abstract: A memory module includes a first memory device, a second memory device, and a processing buffer circuit that is connected to the first memory device and the second memory device (independently of each other) and a host. A processing buffer circuit is provided, which includes a processing circuit and a buffer. The processing circuit processes at least one of data received from the host, data stored in the first memory device, or data stored in the second memory device based on a processing command received from the host. The buffer is configured to store data processed by the processing circuit. The processing buffer circuit is configured to communicate with the host in compliance with a DDR SDRAM standard.

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