公开(公告)号：US10164030B2

公开(公告)日：2018-12-25

申请号：US15604687

申请日：2017-05-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-bum Kim ,  Chul-sung Kim ,  Deok-han Bae ,  Bon-young Koo

IPC: H01L29/41 ,  H01L21/82 ,  H01L27/092 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L29/165 ,  H01L21/8238

Abstract: A semiconductor device may include a substrate including an NMOS region and a PMOS region, and having a protrusion pattern; first and second gate structures respectively formed on the NMOS region and the PMOS region of the substrate, crossing the protrusion pattern, and extending along a first direction that is parallel to an upper surface of the substrate; first and second source/drain regions formed on both sides of the first and second gate structures; and first and second contact plugs respectively formed on the first and second source/drain regions, wherein the first contact plug and the second contact plug are asymmetric. Methods of manufacturing are also provided.

公开(公告)号：US09755076B2

公开(公告)日：2017-09-05

申请号：US15378178

申请日：2016-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok-hoon Kim ,  Jin-bum Kim ,  Kwan-heum Lee ,  Byeong-chan Lee ,  Cho-eun Lee ,  Su-jin Jung

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/417 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/7848 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7856

Abstract: Semiconductor devices include a strain-inducing layer capable of applying a strain to a channel region of a transistor included in a miniaturized electronic device, and a method of manufacturing the semiconductor device. The semiconductor device includes a substrate having a channel region; a pair of source/drain regions provided on the substrate and arranged on both sides of the channel region in a first direction; and a gate structure provided on the channel region and comprising a gate electrode pattern extending in a second direction that is different from the first direction, a gate dielectric layer disposed between the channel region and the gate electrode pattern, and a gate spacer covering respective lateral surfaces of the gate electrode pattern and the gate dielectric layer. At least one of the source/drain regions includes a first strain-inducing layer and a second strain-inducing layer. The first strain-inducing layer is disposed between a lateral surface of the channel region and the second strain-inducing layer and contacts at least a portion of the gate dielectric layer.

公开(公告)号：US09553192B2

公开(公告)日：2017-01-24

申请号：US15189117

申请日：2016-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok-hoon Kim ,  Jin-bum Kim ,  Kwan-heum Lee ,  Byeong-chan Lee ,  Cho-eun Lee ,  Su-jin Jung

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L21/02 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7856

Abstract: Semiconductor devices include a strain-inducing layer capable of applying a strain to a channel region of a transistor included in a miniaturized electronic device, and a method of manufacturing the semiconductor device. The semiconductor device includes a substrate having a channel region; a pair of source/drain regions provided on the substrate and arranged on both sides of the channel region in a first direction; and a gate structure provided on the channel region and comprising a gate electrode pattern extending in a second direction that is different from the first direction, a gate dielectric layer disposed between the channel region and the gate electrode pattern, and a gate spacer covering respective lateral surfaces of the gate electrode pattern and the gate dielectric layer. At least one of the source/drain regions includes a first strain-inducing layer and a second strain-inducing layer. The first strain-inducing layer is disposed between a lateral surface of the channel region and the second strain-inducing layer and contacts at least a portion of the gate dielectric layer.

Abstract translation: 半导体器件包括能够对包括在小型化电子器件中的晶体管的沟道区域施加应变的应变诱导层以及半导体器件的制造方法。 半导体器件包括具有沟道区的衬底; 一对源极/漏极区，设置在所述衬底上并沿第一方向布置在所述沟道区的两侧; 以及栅极结构，设置在所述沟道区上并且包括在与所述第一方向不同的第二方向上延伸的栅极电极图案，设置在所述沟道区域和所述栅极电极图案之间的栅极介电层以及覆盖相应侧面的栅极间隔件 栅电极图案和栅介质层的表面。 源极/漏极区域中的至少一个包括第一应变诱导层和第二应变诱导层。 第一应变诱导层设置在沟道区的侧表面和第二应变诱导层之间，并与栅介质层的至少一部分接触。

公开(公告)号：US11251307B2

公开(公告)日：2022-02-15

申请号：US16120705

申请日：2018-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-jin Park ,  Jin-bum Kim ,  Bong-soo Kim ,  Kyu-pil Lee ,  Hyeong-sun Hong ,  Yoo-sang Hwang

IPC: H01L29/786 ,  H01L29/778 ,  H01L29/88 ,  H01L21/02 ,  H01L29/06 ,  H01L29/16 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/86 ,  H01L29/24

Abstract: A device includes a substrate, a first electrode on the substrate, an insulating pattern on the substrate, a second electrode on an upper end of the insulating pattern, a two-dimensional (2D) material layer on a side surface of the insulating pattern, a gate insulating layer covering the 2D material layer, and a gate electrode contacting the gate insulting layer. The insulating pattern extends from the first electrode in a direction substantially vertical to the substrate. The 2D material layer includes at least one atomic layer of a 2D material that is substantially parallel to the side surface of the insulating pattern.

公开(公告)号：US10600646B2

公开(公告)日：2020-03-24

申请号：US16120728

申请日：2018-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-jin Park ,  Bong-soo Kim ,  Jin-bum Kim ,  Yoo-sang Hwang

IPC: H01L21/02 ,  H01L29/786 ,  H01L29/66 ,  H01L29/778 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/20 ,  H01L29/16 ,  H01L29/24

Abstract: A method of fabricating a device including a two-dimensional (2D) material includes forming an amorphous transition metal oxide structure on a substrate and replacing the amorphous transition metal oxide structure by a transition metal dichalcogenide structure. The transition metal dichalcogenide structure includes atomic layers, that are substantially parallel to a surface of the transition metal dichalcogenide structure.

公开(公告)号：US10515798B2

公开(公告)日：2019-12-24

申请号：US16120775

申请日：2018-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-jin Park ,  Bong-soo Kim ,  Jin-bum Kim ,  Yoo-sang Hwang

IPC: H01L21/02 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/778 ,  H01L29/24 ,  H01L29/16 ,  H01L29/20

Abstract: A method of fabricating a device including a two-dimensional (2D) material includes forming a transition metal oxide pattern on a substrate and forming a transition metal dichalcogenide layer on a top surface and a side surface of a residual portion of the transition metal oxide pattern. The forming the transition metal dichalcogenide layer may include replacing a surface portion of the transition metal oxide pattern with the transition metal dichalcogenide layer. The transition metal dichalcogenide layer includes at least one atomic layer that is substantially parallel to a surface of the residual portion of the transition metal oxide pattern.

公开(公告)号：US10672764B2

公开(公告)日：2020-06-02

申请号：US16174894

申请日：2018-10-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok-hoon Kim ,  Dong-myoung Kim ,  Jin-bum Kim ,  Seung-hun Lee ,  Cho-eun Lee ,  Hyun-jung Lee ,  Sung-uk Jang ,  Edward Namkyu Cho ,  Min-hee Choi

IPC: H01L27/085 ,  H01L29/06 ,  H01L29/423 ,  H01L27/088 ,  H01L21/8234

Abstract: A semiconductor device includes a first region having a first active pattern with first protrusion portions and first recess portions, and a second region having a second active pattern with second protrusion portions and second recess portions. First gate patterns are on the first protrusion portions. Second gate patterns are on the second protrusion portions. A first source/drain region is on one of the first recess portion of the first active pattern between two of the first gate patterns. The first source/drain region has a first reinforcing epitaxial layer at an upper portion thereof. A second source/drain region is on one of the second recess portions of the second active pattern between two of the second gate patterns. The second source/drain region has a second reinforcing epitaxial layer having an epitaxial growth surface that is shaped differently than a first epitaxial growth surface of the first reinforcing epitaxial layer.

公开(公告)号：US20190252376A1

公开(公告)日：2019-08-15

申请号：US16174894

申请日：2018-10-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok-hoon Kim ,  Dong-myoung Kim ,  Jin-bum Kim ,  Seung-hun Lee ,  Cho-eun Lee ,  Hyun-jung Lee ,  Sung-uk Jang ,  Edward Namkyu Cho ,  Min-hee Choi

IPC: H01L27/085 ,  H01L29/423 ,  H01L29/06

Abstract: A semiconductor device includes a first region having a first active pattern with first protrusion portions and first recess portions, and a second region having a second active pattern with second protrusion portions and second recess portions. First gate patterns are on the first protrusion portions. Second gate patterns are on the second protrusion portions. A first source/drain region is on one of the first recess portion of the first active pattern between two of the first gate patterns. The first source/drain region has a first reinforcing epitaxial layer at an upper portion thereof. A second source/drain region is on one of the second recess portions of the second active pattern between two of the second gate patterns. The second source/drain region has a second reinforcing epitaxial layer having an epitaxial growth surface that is shaped differently than a first epitaxial growth surface of the first reinforcing epitaxial layer.

公开(公告)号：US20190074381A1

公开(公告)日：2019-03-07

申请号：US16120726

申请日：2018-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-jin Park ,  Jin-bum Kim ,  Bong-soo Kim ,  Kyu-pil Lee ,  Hyeong-sun Hong ,  Yoo-sang Hwang

IPC: H01L29/786 ,  H01L29/24 ,  H01L29/423 ,  H01L29/78 ,  H01L29/86 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06

Abstract: A device including a two-dimensional (2D) material includes a substrate including a recess recessed from a main surface of the substrate and extending in a first direction, a 2D material pattern on the substrate and intersecting with the recess of the substrate, a gate structure contacting the 2D material pattern and extending in the first direction along the recess of the substrate, a first electrode contacting a first end of the 2D material pattern, and a second electrode contacting a second end of the 2D material pattern. The 2D material pattern extends in a second direction and includes atomic layers that are parallel to a surface of the substrate.

公开(公告)号：US20190074380A1

公开(公告)日：2019-03-07

申请号：US16120705

申请日：2018-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-jin PARK ,  Jin-bum Kim ,  Bong-soo Kim ,  Kyu-pil Lee ,  Hyeong-sun Hong ,  Yoo-sang Hwang

IPC: H01L29/786 ,  H01L29/24 ,  H01L29/423 ,  H01L29/78 ,  H01L29/86 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06

Abstract: A device includes a substrate, a first electrode on the substrate, an insulating pattern on the substrate, a second electrode on an upper end of the insulating pattern, a two-dimensional (2D) material layer on a side surface of the insulating pattern, a gate insulating layer covering the 2D material layer, and a gate electrode contacting the gate insulting layer. The insulating pattern extends from the first electrode in a direction substantially vertical to the substrate. The 2D material layer includes at least one atomic layer of a 2D material that is substantially parallel to the side surface of the insulating pattern.