公开(公告)号：US20160372456A1

公开(公告)日：2016-12-22

申请号：US15155361

申请日：2016-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hyun Yoo ,  Jong-Sung JEON

IPC: H01L27/02 ,  H01L29/06

CPC classification number: H01L27/0266 ,  H01L27/027 ,  H01L29/0642 ,  H01L29/0684

Abstract: A semiconductor device includes a first well in a substrate, a gate structure on the first well, a second well below the gate structure in the first well, a third well in a first side of the gate structure and in the first well to be adjacent to the second well, the third well having a conductivity type different from that of the second well, a fourth well overlapped with the third well, a fifth well in a second side of the gate structure and in the second well, a sixth well below the gate structure and in the second well, the sixth well being adjacent to the fifth well and having an impurity concentration higher than the impurity concentration of the second well, and a first device isolation layer overlapped with the second well and disposed farther away from the gate structure than the fifth well.

Abstract translation: 半导体器件包括衬底中的第一阱，第一阱上的栅极结构，第一阱中的栅极结构下面的第二阱，栅极结构的第一侧中的第三阱以及与第一阱相邻的第一阱 到第二阱，第三阱具有不同于第二阱的导电类型，第四阱与第三阱重叠，第五阱在栅极结构的第二侧中，在第二阱中，第六阱在下面 所述栅极结构，并且在所述第二阱中，所述第六阱与所述第五阱相邻，并且具有高于所述第二阱的杂质浓度的杂质浓度，以及与所述第二阱重叠并且远离所述第二阱的第二阱重叠的第一器件隔离层 门结构比第五井。

公开(公告)号：US20160225896A1

公开(公告)日：2016-08-04

申请号：US14993108

申请日：2016-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Hyun YOO ,  Jin-Hyun NOH ,  Kee-Moon CHUN ,  Jong-Sung JEON

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7816 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/165 ,  H01L29/7835 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device has reduced ON resistance (Ron) as well as a reduced electric field emanating from a current path. The semiconductor device includes a fin pattern, a gate electrode intersecting the fin pattern, a source region which has a first conductivity type and is disposed on one side of the gate electrode, a body region which has a second conductivity type, is situated within the fin pattern under the source region, and extends in a loop around the source region, a drain region which has the first conductivity type and is disposed on the other side of the gate electrode, a field dispersion region which has the second conductivity type and is situated within the fin pattern between the gate electrode and the drain region, and a drift region which has the first conductivity type, is situated within the fin pattern under the drain region and the field dispersion region, and extends in a loop around the drain region and the field dispersion region.

Abstract translation: 半导体器件具有降低的导通电阻（Ron）以及从电流路径发出的减小的电场。 半导体器件包括鳍状图案，与鳍状图案相交的栅极电极，具有第一导电类型并且设置在栅电极的一侧上的源极区域，具有第二导电类型的体区域位于 翅片图案，并且围绕源极区域以环形延伸，具有第一导电类型并设置在栅电极的另一侧的漏极区域，具有第二导电类型的场分散区域并且是 位于栅极电极和漏极区域之间的鳍状图案中，并且具有第一导电类型的漂移区域位于漏极区域和场分散区域下方的鳍状图案内，并且围绕漏极区域以环状延伸 和场分散区域。

公开(公告)号：US20170005162A1

公开(公告)日：2017-01-05

申请号：US15268833

申请日：2016-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Hyun NOH ,  Su-Tae KIM ,  Jae-Hyun YOO ,  Byeong-Ryeol LEE ,  Jong-Sung JEON

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/063 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/165 ,  H01L29/408 ,  H01L29/4238 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/785 ,  H01L29/7851

Abstract: Semiconductor devices include a channel layer on a substrate, the channel layer including a material having a lattice constant different from a lattice constant of the substrate, a first gate electrode on the channel layer, a first source region of a first conductivity type at a first side of the first gate electrode, a first body region of a second conductivity type under the first source region and contacting the first source region, a first drain region of the first conductivity type disposed at a second side of the first gate electrode, a first drift region of the first conductivity type under the first drain region and contacting the first drain region, and a first stud region in the channel layer and the first drift region. The first stud region has an impurity concentration higher than an impurity concentration of the first drift region.

Abstract translation: 半导体器件包括在衬底上的沟道层，沟道层包括具有不同于衬底的晶格常数的晶格常数的材料，沟道层上的第一栅电极，第一导电类型的第一源极区 在所述第一源极区域的第一导电类型的第一主体区域和与所述第一源极区域接触的第一导电类型的第一主体区域，设置在所述第一栅极电极的第二侧的所述第一导电类型的第一漏极区域， 在第一漏区下面的第一导电类型的漂移区，并与第一漏极区以及沟道层和第一漂移区中的第一柱状区域接触。 第一螺柱区域的杂质浓度高于第一漂移区域的杂质浓度。

公开(公告)号：US20170256533A1

公开(公告)日：2017-09-07

申请号：US15603969

申请日：2017-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hyun YOO ,  Jin-Tae KIM ,  Jong-Sung JEON

IPC: H01L27/02 ,  H01L27/06

CPC classification number: H01L27/0266 ,  H01L27/0248 ,  H01L27/0285 ,  H01L27/0288 ,  H01L27/0629

Abstract: An electrostatic discharge (ESD) protection device includes a substrate including a plurality of fins extending in a first direction, with an insulation layer on the fins. A gate electrode extending in a second direction, an electrode pattern of a capacitor, and a resistor are on the insulation layer. A drain is on a first side of the gate electrode, and a source is on a second side of the gate electrode. A connection structure electrically connects the electrode pattern, the gate electrode and the resistor. The electrode pattern is on the first side or the second side of the gate electrode, and the resistor is on the other of the first side or the second side. At least a portion of the resistor extends in the second direction.

公开(公告)号：US20160141388A1

公开(公告)日：2016-05-19

申请号：US14856666

申请日：2015-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kang-Hyun BAEK ,  Kwan-Jae SONG ,  Jong-Sung JEON

IPC: H01L29/66 ,  H01L29/06

CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L29/66818

Abstract: In a method, a dummy gate layer structure and a mask layer are formed on a substrate. The mask layer is patterned to form masks. Spacers are formed on sidewalls of the mask. A dummy gate mask is formed between the spacers. The dummy gate layer structure is patterned using the dummy gate mask to form dummy gate structures. The dummy gate structure is replaced with a gate structure. When the mask is formed, an initial layout of masks extending in a first direction is designed. An offset bias in a second direction is provided for a specific region of the initial layout to design a final layout having a width in the second direction varying along the first direction. The mask layer is patterned according to the final layout to form the masks having a width varying along the first direction.

Abstract translation: 在一种方法中，在基板上形成伪栅极层结构和掩模层。 将掩模层图案化以形成掩模。 垫片形成在面罩的侧壁上。 在间隔件之间形成虚拟栅极掩模。 使用伪栅极掩模对虚拟栅极层结构进行图案化以形成伪栅极结构。 虚拟栅极结构被栅极结构代替。 当形成掩模时，设计沿第一方向延伸的掩模的初始布局。 针对初始布局的特定区域提供第二方向上的偏移偏移，以设计沿着第一方向具有沿第二方向的宽度变化的最终布局。 根据最终布局图案化掩模层以形成具有沿着第一方向变化的宽度的掩模。

公开(公告)号：US20150102394A1

公开(公告)日：2015-04-16

申请号：US14509365

申请日：2014-10-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hyun YOO ,  Jin-Tae KIM ,  Jong-Sung JEON

IPC: H01L27/02 ,  H01L27/06

CPC classification number: H01L27/0266 ,  H01L27/0248 ,  H01L27/0285 ,  H01L27/0288 ,  H01L27/0629

Abstract: An electrostatic discharge (ESD) protection device includes a substrate including a plurality of active fins and a plurality of grooves. The ESD protection device includes an insulation layer on the active fins and the grooves, and a gate electrode on the active fins. The ESD protection device includes a first impurity region adjacent to a first side of the gate electrode, and a second impurity region adjacent to a second side of the gate electrode. The second side of the gate electrode may be arranged opposite to the first side. The ESD protection device includes an electrode pattern of a capacitor overlapping the first impurity region, a resistor overlapping the second impurity region, and a connection structure electrically connecting the electrode pattern, the gate electrode, and the resistor to each other.

Abstract translation: 静电放电（ESD）保护装置包括具有多个活动散热片和多个槽的基板。 ESD保护装置包括有源散热片和沟槽上的绝缘层，以及活性散热片上的栅电极。 ESD保护器件包括与栅极电极的第一侧相邻的第一杂质区域和与栅极电极的第二侧相邻的第二杂质区域。 栅电极的第二侧可以布置成与第一侧相对。 ESD保护装置包括与第一杂质区重叠的电容器的电极图案，与第二杂质区域重叠的电阻器以及将电极图案，栅极电极和电阻器彼此电连接的连接结构。

公开(公告)号：US20150001641A1

公开(公告)日：2015-01-01

申请号：US14282230

申请日：2014-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Hyun YOO ,  Young-Keun LEE ,  Wook LEE ,  Jong-Sung JEON

IPC: H01L29/78

CPC classification number: H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/1033 ,  H01L29/1041 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7836 ,  H01L29/785

Abstract: A transistor and a semiconductor device, the semiconductor device including an active region; a gate electrode on the active region; and a gate dielectric between the gate electrode and the active region, wherein the active region includes a first part overlapped by the gate electrode, and second and third parts facing each other with the first part therebetween, the first part of the active region includes a first portion having a first width and a second portion having a second width, the second width being greater than the first width, and the second portion of the active region is closer to the second part of the active region than to the third part of the active region.

Abstract translation: 一种晶体管和半导体器件，所述半导体器件包括有源区; 有源区上的栅电极; 以及栅电极和有源区之间的栅极电介质，其中所述有源区包括与所述栅电极重叠的第一部分，以及彼此面对的第二部分和第三部分，所述有源区的所述第一部分包括： 具有第一宽度的第一部分和具有第二宽度的第二部分，第二宽度大于第一宽度，并且有源区域的第二部分更接近有源区域的第二部分，而不是第二部分的第三部分 活跃区域。

公开(公告)号：US20140316760A1

公开(公告)日：2014-10-23

申请号：US14254337

申请日：2014-04-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wook LEE ,  Han-Gu KIM ,  Young-Keun LEE ,  Jong-Sung JEON

IPC: G06F17/50

CPC classification number: G06F17/5036

Abstract: A three-dimensional optoelectrical simulation includes generating a process simulation result including a doping profile of a silicon substrate of image sensor, a structure simulation result with respect to a back end of line structure, and a merged result generated by merging a process simulation result and a structure simulation result, selectively extending the merged result to an extended result by using a process simulation result or a structure simulation result, generating a segmented result for each pixel based on a merged result or an extended result, an optical crosstalk simulation result of image sensor based on a structure simulation result and an optical mesh, and a final simulation result including an electrical crosstalk simulation result of the image sensor based on a segmented result for each pixel and an optical crosstalk simulation result.

Abstract translation: 三维光电仿真包括生成包括图像传感器的硅衬底的掺杂分布，相对于线结构的后端的结构模拟结果的过程模拟结果，以及通过将过程模拟结果和 结构模拟结果，通过使用过程模拟结果或结构模拟结果选择性地将合并结果扩展到扩展结果，基于合并结果或扩展结果为每个像素生成分段结果，图像的光学串扰模拟结果 基于结构仿真结果和光学网格的传感器，以及包括基于每个像素的分割结果的图像传感器的电串扰仿真结果和光学串扰仿真结果的最终仿真结果。