公开(公告)号：US09496277B2

公开(公告)日：2016-11-15

申请号：US14723644

申请日：2015-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

IPC: H01L21/336 ,  H01L27/115 ,  H01L29/66 ,  H01L29/792 ,  H01L27/105 ,  H01L21/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/306 ,  H01L21/3213 ,  H01L29/423

CPC classification number: H01L27/11582 ,  H01L21/02524 ,  H01L21/02587 ,  H01L21/02598 ,  H01L21/02675 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/30604 ,  H01L21/32133 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/1158 ,  H01L29/4234 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66666 ,  H01L29/66787 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

Abstract: In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall of each of the single-crystalline semiconductor patterns. The transistors are arranged in a vertical direction of the single-crystalline semiconductor pattern, and thus the memory device may be highly integrated.

公开(公告)号：US20150035061A1

公开(公告)日：2015-02-05

申请号：US14262230

申请日：2014-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang-Seop Yoon ,  Hee-Soo Kang ,  Jong-Wook Lee ,  Soon Cho

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Provided are a multi-gate transistor device and a method for fabricating the same. The method for fabricating the multi-gate transistor device includes forming first and second fins shaped to protrude on a substrate and aligned and extending in a first direction and a trench separating the first and second fins from each other in the first direction between the first and second fins, performing ion implantation of impurities on sidewalls of the trench, forming a field dielectric film filling the trench, forming a recess in the first fin not exposing the field dielectric film, and growing an epitaxial layer in the recess.

Abstract translation: 提供一种多栅极晶体管器件及其制造方法。 制造多栅极晶体管器件的方法包括：形成第一和第二鳍片，其形状突出在基底上并且在第一方向上对准和延伸;以及沟槽，其将第一和第二鳍片沿着第一方向彼此分开， 第二鳍片，在沟槽的侧壁上执行杂质的离子注入，形成填充沟槽的场电介质膜，在第一鳍片中形成不露出场介电膜的凹槽，以及在凹槽中生长外延层。

公开(公告)号：US08906757B2

公开(公告)日：2014-12-09

申请号：US13674386

申请日：2012-11-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeong-Cheol Kim ,  Il-Sup Kim ,  Cheol Kim ,  Jong-Chan Shin ,  Jong-Wook Lee ,  Choong-Ho Lee ,  Si-Young Choi ,  Jong-Seo Hong

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/308 ,  H01L21/033

CPC classification number: H01L27/0886 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L29/16

Abstract: Methods of forming patterns of a semiconductor device are provided. The methods may include forming a hard mask film on a semiconductor substrate. The methods may include forming first and second sacrificial film patterns that are spaced apart from each other on the hard mask film. The methods may include forming a first spacer on opposing sidewalls of the first sacrificial film pattern and a second spacer on opposing sidewalls of the second sacrificial film pattern. The methods may include removing the first and second sacrificial film patterns. The methods may include trimming the second spacer such that a line width of the second spacer becomes smaller than a line width of the first spacer. The methods may include forming first and second hard mask film patterns by etching the hard mask film using the first spacer and the trimmed second spacer as an etch mask.

Abstract translation: 提供了形成半导体器件的图案的方法。 所述方法可以包括在半导体衬底上形成硬掩模膜。 所述方法可以包括形成在硬掩模膜上彼此间隔开的第一和第二牺牲膜图案。 所述方法可以包括在第一牺牲膜图案的相对侧壁上形成第一间隔物，以及在第二牺牲膜图案的相对侧壁上形成第二间隔物。 所述方法可以包括去除第一和第二牺牲膜图案。 所述方法可以包括修整第二间隔物，使得第二间隔物的线宽变得小于第一间隔物的线宽。 所述方法可以包括通过使用第一间隔物和修剪的第二间隔物作为蚀刻掩模蚀刻硬掩模膜来形成第一和第二硬掩模膜图案。

公开(公告)号：US20140080273A1

公开(公告)日：2014-03-20

申请号：US14083971

申请日：2013-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

IPC: H01L27/105 ,  H01L29/66

CPC classification number: H01L27/11582 ,  H01L21/02524 ,  H01L21/02587 ,  H01L21/02598 ,  H01L21/02675 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/30604 ,  H01L21/32133 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/1158 ,  H01L29/4234 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66666 ,  H01L29/66787 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

Abstract: In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall of each of the single-crystalline semiconductor patterns. The transistors are arranged in a vertical direction of the single-crystalline semiconductor pattern, and thus the memory device may be highly integrated.

Abstract translation: 在垂直型存储器件和垂直型存储器件的制造方法中，垂直存储器件包括设置在衬底上的线状绝缘层图形，柱状单晶半导体图案设置在两侧壁上 设置在每个单晶半导体图案的侧壁上的绝缘层图案和晶体管。 晶体管沿着单晶半导体图案的垂直方向排列，因此存储器件可以高度集成。

公开(公告)号：US20130134501A1

公开(公告)日：2013-05-30

申请号：US13750066

申请日：2013-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

IPC: H01L29/78

CPC classification number: H01L29/7827 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7841

Abstract: In a vertical-type semiconductor device, a method of manufacturing the same and a method of operating the same, the vertical-type semiconductor device includes a single-crystalline semiconductor pattern having a pillar shape provided on a substrate, a gate surrounding sidewalls of the single-crystalline semiconductor pattern and having an upper surface lower than an upper surface of the single-crystalline semiconductor pattern, a mask pattern formed on the upper surface of the gate, the mask pattern having an upper surface coplanar with the upper surface of the single-crystalline semiconductor pattern, a first impurity region in the substrate under the single-crystalline semiconductor pattern, and a second impurity region under the upper surface of the single-crystalline semiconductor pattern. The vertical-type pillar transistor formed in the single-crystalline semiconductor pattern may provide excellent electrical properties. The mask pattern is not provided on the upper surface of the single-crystalline semiconductor pattern in the second impurity region, to thereby reduce failures of processes.

Abstract translation: 在垂直型半导体器件中，其制造方法及其操作方法，垂直型半导体器件包括：具有设置在基板上的柱状的单晶半导体图案， 单晶半导体图案，并且具有比单晶半导体图案的上表面低的上表面，形成在栅极的上表面上的掩模图案，所述掩模图案具有与单个半导体图案的上表面共面的上表面 晶体半导体图案，在单晶半导体图案下的衬底中的第一杂质区域和在单晶半导体图案的上表面下方的第二杂质区域。 形成在单晶半导体图案中的垂直型立柱晶体可以提供优异的电性能。 在第二杂质区域中的单晶半导体图案的上表面上没有设置掩模图案，从而减少处理的失败。

公开(公告)号：US20170012054A1

公开(公告)日：2017-01-12

申请号：US15275972

申请日：2016-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/792 ,  H01L21/3213 ,  H01L29/66 ,  H01L29/45 ,  H01L21/285

CPC classification number: H01L27/11582 ,  H01L21/02524 ,  H01L21/02587 ,  H01L21/02598 ,  H01L21/02675 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/30604 ,  H01L21/32133 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/1158 ,  H01L29/4234 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66666 ,  H01L29/66787 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

Abstract: In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall of each of the single-crystalline semiconductor patterns. The transistors are arranged in a vertical direction of the single-crystalline semiconductor pattern, and thus the memory device may be highly integrated.

Abstract translation: 在垂直型存储器件和垂直型存储器件的制造方法中，垂直存储器件包括设置在衬底上的线状绝缘层图形，柱状单晶半导体图案设置在两侧壁上 设置在每个单晶半导体图案的侧壁上的绝缘层图案和晶体管。 晶体管沿着单晶半导体图案的垂直方向排列，因此存储器件可以高度集成。

公开(公告)号：US09029939B2

公开(公告)日：2015-05-12

申请号：US13750066

申请日：2013-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

IPC: H01L29/78 ,  H01L27/108 ,  H01L29/66

CPC classification number: H01L29/7827 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7841

Abstract: In a vertical-type semiconductor device, a method of manufacturing the same and a method of operating the same, the vertical-type semiconductor device includes a single-crystalline semiconductor pattern having a pillar shape provided on a substrate, a gate surrounding sidewalls of the single-crystalline semiconductor pattern and having an upper surface lower than an upper surface of the single-crystalline semiconductor pattern, a mask pattern formed on the upper surface of the gate, the mask pattern having an upper surface coplanar with the upper surface of the single-crystalline semiconductor pattern, a first impurity region in the substrate under the single-crystalline semiconductor pattern, and a second impurity region under the upper surface of the single-crystalline semiconductor pattern. The vertical-type pillar transistor formed in the single-crystalline semiconductor pattern may provide excellent electrical properties. The mask pattern is not provided on the upper surface of the single-crystalline semiconductor pattern in the second impurity region, to thereby reduce failures of processes.

Abstract translation: 在垂直型半导体器件中，其制造方法及其操作方法，垂直型半导体器件包括：具有设置在基板上的柱状的单晶半导体图案， 单晶半导体图案，并且具有比单晶半导体图案的上表面低的上表面，形成在栅极的上表面上的掩模图案，所述掩模图案具有与单个半导体图案的上表面共面的上表面 晶体半导体图案，在单晶半导体图案下的衬底中的第一杂质区域和在单晶半导体图案的上表面下方的第二杂质区域。 形成在单晶半导体图案中的垂直型立柱晶体可以提供优异的电性能。 在第二杂质区域中的单晶半导体图案的上表面上没有设置掩模图案，从而减少处理的失败。

公开(公告)号：US20150076617A1

公开(公告)日：2015-03-19

申请号：US14548871

申请日：2014-11-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myeong-Cheol Kim ,  Il-Sup Kim ,  Cheol Kim ,  Jong-Chan Shin ,  Jong-Wook Lee ,  Choong-Ho Lee ,  Si-Young Choi ,  Jong-Seo Hong

IPC: H01L27/088 ,  H01L29/16

CPC classification number: H01L27/0886 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L29/16

Abstract: Methods of forming patterns of a semiconductor device are provided. The methods may include forming a hard mask film on a semiconductor substrate. The methods may include forming first and second sacrificial film patterns that are spaced apart from each other on the hard mask film. The methods may include forming a first spacer on opposing sidewalls of the first sacrificial film pattern and a second spacer on opposing sidewalls of the second sacrificial film pattern. The methods may include removing the first and second sacrificial film patterns. The methods may include trimming the second spacer such that a line width of the second spacer becomes smaller than a line width of the first spacer. The methods may include forming first and second hard mask film patterns by etching the hard mask film using the first spacer and the trimmed second spacer as an etch mask.

Abstract translation: 提供了形成半导体器件的图案的方法。 所述方法可以包括在半导体衬底上形成硬掩模膜。 所述方法可以包括形成在硬掩模膜上彼此间隔开的第一和第二牺牲膜图案。 所述方法可以包括在第一牺牲膜图案的相对侧壁上形成第一间隔物，以及在第二牺牲膜图案的相对侧壁上形成第二间隔物。 所述方法可以包括去除第一和第二牺牲膜图案。 所述方法可以包括修整第二间隔物，使得第二间隔物的线宽变得小于第一间隔物的线宽。 所述方法可以包括通过使用第一间隔物和修剪的第二间隔物作为蚀刻掩模蚀刻硬掩模膜来形成第一和第二硬掩模膜图案。

公开(公告)号：US20130143372A1

公开(公告)日：2013-06-06

申请号：US13674386

申请日：2012-11-12

Applicant: Samsung Electronics Co., Ltd

Inventor： Myeong-Cheol KIM ,  Il-Sup Kim ,  Cheol Kim ,  Jong-Chan Shin ,  Jong-Wook Lee ,  Choong-Ho Lee ,  Si-Young Choi ,  Jong-Seo Hong

IPC: H01L21/308

CPC classification number: H01L27/0886 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L29/16

Abstract: Methods of forming patterns of a semiconductor device are provided. The methods may include forming a hard mask film on a semiconductor substrate. The methods may include forming first and second sacrificial film patterns that are spaced apart from each other on the hard mask film. The methods may include forming a first spacer on opposing sidewalls of the first sacrificial film pattern and a second spacer on opposing sidewalls of the second sacrificial film pattern. The methods may include removing the first and second sacrificial film patterns. The methods may include trimming the second spacer such that a line width of the second spacer becomes smaller than a line width of the first spacer. The methods may include forming first and second hard mask film patterns by etching the hard mask film using the first spacer and the trimmed second spacer as an etch mask.

公开(公告)号：US20190035809A1

公开(公告)日：2019-01-31

申请号：US16139285

申请日：2018-09-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

IPC: H01L27/11582 ,  H01L29/792 ,  H01L21/02 ,  H01L29/66 ,  H01L29/45 ,  H01L29/423 ,  H01L27/11578 ,  H01L27/11568 ,  H01L27/105 ,  H01L21/3213 ,  H01L21/306 ,  H01L21/285 ,  H01L21/28 ,  H01L27/1158

Abstract: In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall of each of the single-crystalline semiconductor patterns. The transistors are arranged in a vertical direction of the single-crystalline semiconductor pattern, and thus the memory device may be highly integrated.