公开(公告)号：US20240128159A1

公开(公告)日：2024-04-18

申请号：US18367549

申请日：2023-09-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minjae JEONG ,  Jaehee CHO ,  Geonwoo NAM ,  Jungho DO ,  Jisu YU ,  Hyeongyu YOU ,  Seungyoung LEE

IPC: H01L23/48 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L21/823807 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: An integrated circuit including a standard cell including: a metal layer including a pattern extending in a first horizontal direction and a plurality of tracks spaced apart from one another in a second horizontal direction, wherein the plurality of tracks include a plurality of cell tracks and one power distribution network (PDN) track, wherein cell patterns are formed on the plurality of cell tracks, and a PDN pattern or a routing pattern is formed on the one power distribution network (PDN) track, wherein a first pattern is spaced apart from a cell boundary of the standard cell by a first length and is formed on a first cell track among the plurality of cell tracks, and wherein a second pattern is spaced apart from a cell boundary of the standard cell by a second length and is formed on a second cell track among the plurality of cell tracks.

公开(公告)号：US20230142050A1

公开(公告)日：2023-05-11

申请号：US17984417

申请日：2022-11-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeongyu YOU ,  Jungho DO ,  Sangdo PARK ,  Jaewoo SEO ,  Jisu YU ,  Minjae JEONG ,  Dayeon CHO

IPC: H01L27/06 ,  H01L49/02 ,  H01L27/02

CPC classification number: H01L27/06 ,  H01L28/88 ,  H01L27/0207

Abstract: An integrated circuit including a plurality of stacked metal layers and a method of manufacturing the integrated circuit are provided. The method includes: providing a plurality of standard cells, each of which includes cell patterns respectively formed on the plurality of metal layers; and forming, on a particular metal layer among the plurality of metal layers which includes patterns extending in a first direction that are respectively formed on a plurality of tracks that are spaced apart from each other in a second direction, an additional pattern between adjacent patterns formed on a particular track of the plurality of tracks based on an interval between the adjacent patterns exceeding a reference value.

公开(公告)号：US20240055431A1

公开(公告)日：2024-02-15

申请号：US18222734

申请日：2023-07-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minjae JEONG ,  Jisu YU ,  Geonwoo NAM ,  Jungho DO ,  Hyeongyu YOU ,  Jaehee CHO

IPC: H01L27/092 ,  H01L23/528 ,  G06F30/392

CPC classification number: H01L27/0922 ,  H01L23/528 ,  G06F30/392

Abstract: An integrated circuit includes a first cell disposed in a first row and a second row, which are adjacent to each other and extend in a first direction, and including a plurality of first threshold voltage devices and at least one second cell disposed adjacent to the first cell in at least one of the first row and the second row and including at least one second threshold voltage device, wherein the plurality of first threshold voltage devices include at least one first device configured to perform a first function in the first row and at least one second device configured to perform a second function, which is different from the first function, in the second row.

公开(公告)号：US20220208757A1

公开(公告)日：2022-06-30

申请号：US17562428

申请日：2021-12-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungho DO ,  Sanghoon BAEK

IPC: H01L27/06 ,  H01L23/528

Abstract: An integrated circuit device is provided. The integrated circuit device includes: a substrate with a first active area and a second active area spaced apart from each other in a first horizontal direction; a plurality of normal cells arranged on a first surface of the substrate; a power wiring structure arranged on a second surface of the substrate; and a power gating cell arranged on the first surface of the substrate. The power gating cell includes: a sleep control transistor arranged in the first active area; and a through via penetrating the second active area of the substrate. The power gating cell is configured to provide a virtual power voltage to the plurality of normal cells through a virtual power line based on a power voltage supplied from the power wiring structure through the through via and a power line.

公开(公告)号：US20220059460A1

公开(公告)日：2022-02-24

申请号：US17323407

申请日：2021-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungho DO ,  Sanghoon BAEK

IPC: H01L23/528 ,  H01L27/092 ,  H01L27/02 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes a substrate having an active region, a first group of standard cells arranged in a first row on the active region of the substrate and having a first height defined in a column direction, a second group of standard cells arranged in a second row on the active region of the substrate, and having a second height, and a plurality of power lines extending in a row direction and respectively extending along boundaries of the first and the second groups of standard cells. The first and second groups of standard cells each further include a plurality of wiring lines extending in the row direction and arranged in the column direction, and at least some of wiring lines in at least one standard cell of the first and second groups of standard cells are arranged at different spacings and/or pitches.

公开(公告)号：US20240088039A1

公开(公告)日：2024-03-14

申请号：US18512527

申请日：2023-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungho DO ,  Sanghoon BAEK

IPC: H01L23/528 ,  H01L27/02 ,  H01L27/092 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L23/5286 ,  H01L27/0207 ,  H01L27/092 ,  H01L29/42392 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate having an active region, a first group of standard cells arranged in a first row on the active region of the substrate and having a first height defined in a column direction, a second group of standard cells arranged in a second row on the active region of the substrate, and having a second height, and a plurality of power lines extending in a row direction and respectively extending along boundaries of the first and the second groups of standard cells. The first and second groups of standard cells each further include a plurality of wiring lines extending in the row direction and arranged in the column direction, and at least some of wiring lines in at least one standard cell of the first and second groups of standard cells are arranged at different spacings and/or pitches.

公开(公告)号：US20210050854A1

公开(公告)日：2021-02-18

申请号：US17088819

申请日：2020-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejoong SONG ,  Jungho DO ,  Seungyoung LEE ,  Jonghoon JUNG

IPC: H03K19/17724 ,  H01L27/02 ,  H01L29/06 ,  H01L23/528 ,  H01L29/423 ,  H01L27/088

Abstract: A semiconductor device is provided. The semiconductor device includes first and second logic cells adjacent to each other on a substrate, and a mixed separation structure extending in a first direction between the first and second logic cells. Each logic cell includes first and second active fins that protrude from the substrate, the first and second active fins extending in a second direction intersecting the first direction and being spaced apart from each other in the first direction, and gate electrodes extending in the first direction and spanning the first and second active fins, and having a gate pitch. The mixed separation structure includes a first separation structure separating the first active fin of the first logic cell from the first active fin of the second logic cell; and a second separation structure on the first separation structure. A width of the first separation structure is greater than the gate pitch.

公开(公告)号：US20200219974A1

公开(公告)日：2020-07-09

申请号：US16819823

申请日：2020-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungho DO

IPC: H01L29/06 ,  H01L29/78 ,  H01L23/522 ,  H01L29/08 ,  H01L27/092 ,  H01L29/66 ,  H01L27/24

Abstract: A cell architecture is provided. A cell architecture including a vertical field effect transistor (VFET) having at least two fins serving as a vertical channel, a gate including a first gate portion surrounding the first fin, a second gate portion surrounding the second fin, and a third gate portion providing connection therebetween, and a top source/drain (S/D) including a first top S/D portion on the first fin and a second top S/D portion on the second fin, a gate contact structure connected to the third gate portion, a top S/D contact structure connected to one of the first top S/D portion or the second top S/D portion and serving as a horizontal conductive routing layer; and metal patterns on the gate contact structure and the top S/D contact structure and connected thereto through vias, and serving as a vertical conductive routing layer may be provided.

公开(公告)号：US20200076436A1

公开(公告)日：2020-03-05

申请号：US16677165

申请日：2019-11-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejoong SONG ,  Jungho DO ,  Seungyoung LEE ,  Jonghoon JUNG

IPC: H03K19/177 ,  H01L27/02 ,  H01L29/06 ,  H01L23/528 ,  H01L29/423 ,  H01L27/088

Abstract: A semiconductor device is provided. The semiconductor device includes first and second logic cells adjacent to each other on a substrate, and a mixed separation structure extending in a first direction between the first and second logic cells. Each logic cell includes first and second active fins that protrude from the substrate, the first and second active fins extending in a second direction intersecting the first direction and being spaced apart from each other in the first direction, and gate electrodes extending in the first direction and spanning the first and second active fins, and having a gate pitch. The mixed separation structure includes a first separation structure separating the first active fin of the first logic cell from the first active fin of the second logic cell; and a second separation structure on the first separation structure. A width of the first separation structure is greater than the gate pitch.

公开(公告)号：US20240250028A1

公开(公告)日：2024-07-25

申请号：US18397483

申请日：2023-12-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungho DO ,  Jisu Yu ,  Hyeongyu You ,  Seungyoung Lee ,  Minjae Jeong

IPC: H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/5286 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/4175 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: An integrated circuit may include gate electrodes including first and second gate electrodes being apart in a first direction and third and fourth gate electrodes being apart in the first direction. The second and third gate electrodes receive a first control signal, and the first and fourth gate electrodes receive a second control signal. The integrated circuit further includes a first drain region between the first and second gate electrodes and a second drain region between the third and fourth gate electrodes, wherein the first and second drain regions are electrically connected to each other. The integrated circuit includes a front-side wiring layer connected to at least one of the first and second drain regions and the first to fourth gate electrodes, and a backside wiring layer connected to at least another one of the first and second drain regions and the first to fourth gate electrodes.