公开(公告)号：US20240306404A1

公开(公告)日：2024-09-12

申请号：US18495519

申请日：2023-10-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Geun CHOI ,  Ki Seok LEE ,  Keun Nam KIM ,  Seok Han PARK ,  Bo Won YOO ,  Jin Woo HAN

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B12/00

CPC classification number: H10B80/00 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B12/33 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: A semiconductor memory device including an active pattern on a first substrate and comprising a first and second surfaces opposite to each other in a first direction, a data storage pattern between the active pattern and the first substrate and connected to a first surface of the active pattern, a bit line on the active pattern, connected to a second surface of the active pattern, and extending in a second direction, a word line on a sidewall of the active pattern, a second substrate, a peripheral gate structure on a first surface of the second substrate, a first connection wiring structure on the first surface of the second substrate and connected to the peripheral gate structure and bit line, a second connection wiring structure on a second surface of the second substrate and a through via penetrating the second substrate and connecting the first and second connection wiring structures.

公开(公告)号：US20230139252A1

公开(公告)日：2023-05-04

申请号：US17881032

申请日：2022-08-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok Hwan LEE ,  Ki Seok LEE ,  Sang Ho LEE

IPC: H01L27/108 ,  H01L23/528

Abstract: A semiconductor device includes a device isolation layer defining a cell active area in a substrate. A plurality of buried contacts is electrically connected with the substrate and arranged in a first direction. A bit line structure extends in a second direction between adjacent buried contacts of the plurality of buried contacts. The bit line structure includes a bit line pass portion and a bit line contact portion. The bit line structure is electrically connected with the cell active area. A first buffer pattern is disposed between the substrate and the bit line pass portion. The first buffer pattern has a T-shape in a cross-section taken along the first direction.

公开(公告)号：US20210098460A1

公开(公告)日：2021-04-01

申请号：US16860276

申请日：2020-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Ho LEE ,  Eun A KIM ,  Ki Seok LEE ,  Jay-Bok CHOI ,  Keun Nam KIM ,  Yong Seok AHN ,  Jin-Hwan CHUN ,  Sang Yeon HAN ,  Sung Hee HAN ,  Seung Uk HAN ,  Yoo Sang HWANG

IPC: H01L27/108 ,  H01L23/528

Abstract: A semiconductor device includes a device isolation layer defining first and second active regions, a buried contact connected to the second active region, and first and second bit line structures disposed on the first and second active regions. Each of the first and second bit line structures comprises a bit line contact part and a bit line pass part. The bit line contact part is electrically connected to the first active region. The bit line pass part is disposed on the device isolation layer. A height of a lowest part of the buried contact is smaller than a height of a lowest part of the bit line pass part. The height of the lowest part of the buried contact is greater than a height of a lowest part of the bit line contact part. A lower end of the bit line pass part is buried in the second active region.

公开(公告)号：US20240334673A1

公开(公告)日：2024-10-03

申请号：US18518687

申请日：2023-11-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Seok LEE ,  Hong Jun LEE ,  Hyun Geun CHOI ,  Keun Nam KIM ,  In Cheol NAM ,  Bo Won YOO ,  Jin Woo HAN

IPC: H10B12/00

CPC classification number: H10B12/038 ,  H10B12/482 ,  H10B12/488

Abstract: A semiconductor device includes a lower substrate, a memory cell structure including a wordline on the lower substrate, a bitline disposed on the lower substrate and intersecting the wordline, and a cell capacitor connected to the lower substrate, an upper substrate having a back side adjacent to the lower substrate and a front side opposite to the back side, a circuit element disposed on the front side of the upper substrate and overlapping the memory cell structure in a vertical direction, and a through via penetrating the upper substrate and electrically connecting the memory cell structure and the circuit element with each other.

公开(公告)号：US20210246044A1

公开(公告)日：2021-08-12

申请号：US17229031

申请日：2021-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Wook JUNG ,  Dong Oh KIM ,  Seok Han PARK ,  Chan Sic YOON ,  Ki Seok LEE ,  Ho In LEE ,  Ju Yeon JANG ,  Je Min PARK ,  Jin Woo HONG

IPC: C01G23/053

Abstract: A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.

公开(公告)号：US20170309469A1

公开(公告)日：2017-10-26

申请号：US15381135

申请日：2016-12-16

Applicant: Samsung Electronics Co., Ltd.,

Inventor： Chan Sic YOON ,  Ki Seok LEE ,  Dong Oh KIM ,  Yong Jae KIM

IPC: H01L21/027 ,  G03F1/38 ,  H01L21/02

CPC classification number: H01L21/027 ,  G03F1/38 ,  H01L21/02107 ,  H01L21/02697 ,  H01L27/0207 ,  H01L27/10888

Abstract: Methods for manufacturing a semiconductor device include forming a gate line extending in a first direction in a substrate, and an impurity region on a side surface of the gate line, forming an insulating film pattern on the substrate, the insulating film pattern extending in the first direction and comprising a first through-hole that is configured to expose the impurity region, forming a barrier metal layer on the first through-hole, forming a conductive line contact that fills the first through-hole and that is electrically connected to the impurity region, forming a first mask pattern on the conductive line contact and the insulating film pattern, the first mask pattern extending in a second direction that is different from the first direction and the first mask pattern comprising a first opening, and removing corners of the barrier metal layer by partially etching the barrier metal layer.

公开(公告)号：US20170194261A1

公开(公告)日：2017-07-06

申请号：US15258138

申请日：2016-09-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chan Sic YOON ,  Ki Seok LEE

IPC: H01L23/535 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L23/535 ,  H01L23/485 ,  H01L27/10814 ,  H01L29/0649 ,  H01L29/4236

Abstract: A semiconductor device includes a first contact plug on a substrate, a first lower electrode disposed on the first contact plug and extended in a thickness direction of the substrate, a first supporter pattern on the first lower electrode and including an upper surface and a lower surface, the upper surface of the first supporter pattern being higher than a top surface of the first lower electrode, a dielectric film on the first lower electrode, the upper surface of the first supporter pattern and the lower surface of the first supporter pattern and an upper electrode disposed on the dielectric film.

公开(公告)号：US20240357795A1

公开(公告)日：2024-10-24

申请号：US18513011

申请日：2023-11-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae Jin PARK ,  Hui-Jung KIM ,  Sang Jae PARK ,  Ki Seok LEE ,  Myeong-Dong LEE

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/0335

Abstract: There is provided a semiconductor memory device comprising: a substrate; a base insulating film on an upper surface of the substrate; a plurality of first conductive patterns on the base insulating film and spaced apart from each other, wherein the plurality of first conductive patterns extend in a first direction; a spacer structure on a side surface of each of the plurality of first conductive patterns; a barrier metal film on a side surface of the spacer structure, wherein the barrier metal film extends through the base insulating film to be electrically connected to the substrate; a filling metal film on the barrier metal film, wherein the filling metal film fills at least a portion of a space between adjacent ones of the plurality of first conductive patterns; and a capacitor structure on the filling metal film, wherein the capacitor structure is electrically connected to the filling metal film.

公开(公告)号：US20180226411A1

公开(公告)日：2018-08-09

申请号：US15828934

申请日：2017-12-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Wook JUNG ,  Dong Oh KIM ,  Seok Han PARK ,  Chan Sic YOON ,  Ki Seok LEE ,  Ho In LEE ,  Ju Yeon JANG ,  Je Min PARK ,  Jin Woo HONG

IPC: H01L27/11 ,  H01L27/092 ,  H01L27/108 ,  H01L21/8238 ,  H01L29/10

CPC classification number: H01L27/1104 ,  H01L21/823807 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/10852 ,  H01L27/10867 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L29/1029

Abstract: A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.

公开(公告)号：US20240334682A1

公开(公告)日：2024-10-03

申请号：US18522932

申请日：2023-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bo Won YOO ,  Seok Han PARK ,  Ki Seok LEE ,  Hyun Geun CHOI ,  Jin Woo HAN

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/09 ,  H10B12/33 ,  H10B12/50

Abstract: A semiconductor memory device with improved integration and electrical characteristics. The semiconductor memory device includes a peri-gate structure, a first peri-connecting structure on the peri-gate structure, a data storage pattern on the first peri-connecting structure, an active pattern that includes a first surface and a second surface opposite to each other in a first direction, and a first side wall and a second side wall opposite to each other in a second direction, the first surface of the active pattern connected to the data storage pattern and facing a substrate, a bit line on the active pattern, connected to the second surface of the active pattern, and extends in the second direction, a word line on the first side wall of the active pattern and extending in a third direction, a second peri-connecting structure connected to the bit line and a connecting pad connected to the second peri-connecting wiring.