公开(公告)号：US20240324237A1

公开(公告)日：2024-09-26

申请号：US18608149

申请日：2024-03-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonil Lee ,  Kyunghwan Lee

IPC: H10B53/20 ,  H01L21/28 ,  H01L29/51 ,  H01L29/78 ,  H10B51/10 ,  H10B51/20 ,  H10B51/40 ,  H10B53/10 ,  H10B53/40

CPC classification number: H10B53/20 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/78391 ,  H10B51/10 ,  H10B51/20 ,  H10B51/40 ,  H10B53/10 ,  H10B53/40

Abstract: A three-dimensional (3D) semiconductor memory device includes a plurality of memory cells stacked in a vertical direction, each of the plurality of memory cells including a cell transistor and a cell capacitor. The cell capacitor includes a first electrode connected to a first source/drain region of the cell transistor, wherein a through hole is formed in the first electrode and the inner surface of the first electrode is formed in a shape having concave portions and convex portions in plan view, a capacitor insulating layer in the through hole, and a second electrode in the capacitor insulating layer and filling the through hole.

公开(公告)号：US20240324234A1

公开(公告)日：2024-09-26

申请号：US18430291

申请日：2024-02-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonil Lee ,  Kyunghwan Lee ,  Youngin Goh ,  Yukio Hayakawa

IPC: H10B51/20 ,  H10B51/30

CPC classification number: H10B51/20 ,  H10B51/30

Abstract: A 3D FeRAM is provided. The 3D FeRAM includes a semiconductor patterns stacked in a vertical direction on a substrate and spaced apart from each other in a first horizontal direction, bit lines on first side surface of the semiconductor patterns, extending in the first horizontal direction, and spaced apart from each other in the vertical direction, first electrodes on second side surfaces of the semiconductor patterns and spaced apart from each other in both the vertical direction and the first horizontal direction, a ferroelectric layer on the first electrodes, second electrodes on the ferroelectric layers, extending in the first horizontal direction, and spaced apart from each other in the vertical direction, and word lines between two adjacent semiconductor patterns extending in the vertical direction.

公开(公告)号：US12029029B2

公开(公告)日：2024-07-02

申请号：US17716215

申请日：2022-04-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwan Lee ,  Yongseok Kim ,  Hyuncheol Kim ,  Dongsoo Woo ,  Sungwon Yoo

IPC: H10B12/00 ,  H01L29/423 ,  H01L29/792

CPC classification number: H10B12/50 ,  H01L29/4234 ,  H01L29/7926

Abstract: A semiconductor memory device includes a semiconductor substrate a gate structure extending in a vertical direction on the semiconductor device, a plurality of charge trap layers spaced apart from each other in the vertical direction and each having a horizontal cross-section with a first ring shape surrounding the gate structure, a plurality of semiconductor patterns spaced apart from each other in the vertical direction and each having a horizontal cross-section with a second ring shape surrounding the plurality of charge trap layers, a source region and a source line at one end of each of the plurality of semiconductor patterns in a horizontal direction, and a drain region and a drain line at an other end of each of the plurality of semiconductor patterns in the horizontal direction. The gate structure may include a gate insulation layer and a gate electrode layer.

公开(公告)号：US12016188B2

公开(公告)日：2024-06-18

申请号：US17840213

申请日：2022-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuncheol Kim ,  Yongseok Kim ,  Dongsoo Woo ,  Kyunghwan Lee

IPC: G11C13/00 ,  H10K10/50 ,  H10K19/00 ,  H10K85/20

CPC classification number: H10K19/202 ,  G11C13/0014 ,  G11C13/0069 ,  H10K10/50 ,  H10K85/221

Abstract: A semiconductor memory device includes a plurality of semiconductor patterns extending in a first horizontal direction and separated from each other in a second horizontal direction and a vertical direction, each semiconductor pattern including a first source/drain area, a channel area, and a second source/drain area arranged in the first horizontal direction; a plurality of gate insulating layers covering upper surfaces or side surfaces of the channel areas; a plurality of word lines on the upper surfaces or the side surfaces of the channel areas; and a plurality of resistive switch units respectively connected to first sidewalls of the semiconductor patterns, extending in the first horizontal direction, and separated from each other in the second horizontal direction and the vertical direction, each resistive switch unit including a first electrode, a second electrode, and a resistive switch material layer between the first and second electrodes and including carbon nanotubes.

公开(公告)号：US11670679B2

公开(公告)日：2023-06-06

申请号：US17225716

申请日：2021-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwan Lee ,  Yongseok Kim ,  Hyuncheol Kim ,  Sungwon Yoo ,  Jaeho Hong

IPC: H01L29/00 ,  H01L29/10 ,  H01L29/786 ,  H01L29/06

CPC classification number: H01L29/1033 ,  H01L29/0615 ,  H01L29/7869 ,  H01L29/78642

Abstract: A semiconductor device includes a gate electrode on a substrate, a channel surrounding sidewalls of the gate electrode on the substrate, and source/drain electrodes on the substrate at opposite sides of the gate electrode in a first direction parallel to an upper surface of the substrate. A thickness of the channel from the gate electrode to the source/drain electrodes in a horizontal direction parallel to the upper surface of the substrate is not constant but varies in a vertical direction perpendicular to the upper surface of the substrate.

公开(公告)号：US20230112070A1

公开(公告)日：2023-04-13

申请号：US17836228

申请日：2022-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjun Lee ,  Yongseok Kim ,  Hyuncheol Kim ,  Jongman Park ,  Dongsoo Woo ,  Kyunghwan Lee

IPC: G11C11/22 ,  G11C5/06

Abstract: Provided is a memory device. The memory device may include a substrate, a ferroelectric field effect transistor disposed on the substrate, a first channel contacting a gate structure of the ferroelectric field effect transistor and extending in a vertical direction from the gate structure of the ferroelectric field effect transistor, a selection word line disposed at one side of the first channel, a first gate dielectric layer disposed between the first channel and the selection word line, and a cell word line disposed on top of the first channel.

公开(公告)号：US10978480B2

公开(公告)日：2021-04-13

申请号：US16856663

申请日：2020-04-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwan Lee ,  Yongseok Kim ,  Byoung-Taek Kim ,  Tae Hun Kim ,  Dongkyun Seo ,  Junhee Lim

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L29/51 ,  H01L29/423 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11524

Abstract: A three-dimensional semiconductor memory device includes an electrode structure including gate electrodes and insulating layers, which are alternately stacked on a substrate, a semiconductor pattern extending in a first direction substantially perpendicular to a top surface of the substrate and penetrating the electrode structure, a tunnel insulating layer disposed between the semiconductor pattern and the electrode structure, a blocking insulating layer disposed between the tunnel insulating layer and the electrode structure, and a charge storing layer disposed between the blocking insulating layer and the tunnel insulating layer. The charge storing layer includes a plurality of first charge trap layers having a first energy band gap, and a second charge trap layer having a second energy band gap larger than the first energy band gap. The first charge trap layers are embedded in the second charge trap layer between the gate electrodes and the semiconductor pattern.

公开(公告)号：US12279435B2

公开(公告)日：2025-04-15

申请号：US17683460

申请日：2022-03-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwan Lee ,  Yongseok Kim ,  Hyuncheol Kim ,  Jongman Park ,  Dongsoo Woo

IPC: H10B51/20 ,  H10B51/10 ,  H10B51/40

Abstract: A semiconductor device includes first conductive lines provided on a substrate and spaced apart from each other in a first direction perpendicular to a top surface of the substrate, second conductive lines spaced apart from the first conductive lines in a second direction parallel to the top surface of the substrate, a gate electrode disposed between the first and second conductive lines and extended in the first direction, a plurality of channel patterns provided to enclose a side surface of the gate electrode and spaced apart from each other in the first direction, a ferroelectric pattern between each of the channel patterns and the gate electrode, and a gate insulating pattern between each of the channel patterns and the ferroelectric pattern. Each of the channel patterns is connected to a corresponding one of the first conductive lines and a corresponding one of the second conductive lines.

公开(公告)号：US12213302B2

公开(公告)日：2025-01-28

申请号：US17725069

申请日：2022-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwan Lee ,  Yongseok Kim ,  Ilgweon Kim ,  Hyeoungwon Seo ,  Sungwon Yoo ,  Jaeho Hong

IPC: H10B12/00

Abstract: A semiconductor memory device includes a word line extending in a vertical direction, a semiconductor pattern having a ring-shaped horizontal cross-section that extends around the word line, a bit line disposed at a first end of the semiconductor pattern, and a capacitor structure disposed at second end of the semiconductor pattern. The capacitor structure includes a lower electrode layer electrically connected to the second end of the semiconductor pattern, having a ring-shaped horizontal cross-section, and including a connector extending in the vertical direction. A first segment extends in a horizontal direction from an upper end of the connector, and a second segment extends in the horizontal direction from a lower end of the connector. An upper electrode layer surrounded by the lower electrode layer, extends in the vertical direction, and a capacitor dielectric layer is between the lower electrode layer and the upper electrode layer.

公开(公告)号：US20240324239A1

公开(公告)日：2024-09-26

申请号：US18612011

申请日：2024-03-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daewon Ha ,  Kyunghwan Lee ,  Myunghun Woo

IPC: H10B53/30 ,  G11C5/06 ,  H01L21/28 ,  H01L29/51 ,  H01L29/78 ,  H10B51/10 ,  H10B51/30 ,  H10B53/10

CPC classification number: H10B53/30 ,  G11C5/063 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/78391 ,  H10B51/10 ,  H10B51/30 ,  H10B53/10

Abstract: A semiconductor memory device includes a plurality of memory cells each including a first vertical channel transistor (VCT) and a second VCT arranged in a vertical direction and connected to each other in series, the plurality of memory cells respectively including a plurality of ferroelectric capacitors connected to the second VCT in parallel and arranged in the vertical direction, wherein the plurality of memory cells are arranged in columns and rows in a first horizontal direction and a second horizontal direction that is different from the first horizontal direction.