公开(公告)号：US20150155210A1

公开(公告)日：2015-06-04

申请号：US14337571

申请日：2014-07-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byung Joon LEE ,  Masato KAJINAMI ,  Yoshiaki YUKIMORI ,  Sang-Yoon KIM ,  Hui-Jae KIM ,  Byeong-Kuk PARK ,  Seung Dae SEOK ,  Jae Bong SHIN ,  Byeong Kap CHOI

IPC: H01L21/66 ,  H01L21/67 ,  H01L23/00

CPC classification number: H01L21/67259 ,  H01L21/67109 ,  H01L21/67144 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/73204 ,  H01L2224/75502 ,  H01L2224/7565 ,  H01L2224/75753 ,  H01L2224/75824 ,  H01L2224/7598 ,  H01L2224/81127 ,  H01L2224/81204 ,  H01L2224/81801 ,  H01L2224/83127 ,  H01L2224/83204 ,  H01L2224/8385 ,  H01L2224/92125 ,  H05K13/046 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A semiconductor manufacturing apparatus may include: a pickup unit configured to pick up a chip in a first region of the semiconductor manufacturing apparatus; a bonding head configured to receive the picked-up chip and configured to move from the first region to a top of a circuit board in a second region of the semiconductor manufacturing apparatus; and/or an optical unit configured to detect a bonding position on the circuit board while moving from the first region to the second region. A semiconductor manufacturing apparatus may include: a bonding head including a heater for heating a chip and bonding the chip onto a circuit board; and/or a cooling block, adjacent to the heater, through which cooling liquid flows. The cooling liquid may be removed from the cooling block while the heater generates heat. The cooling liquid may be supplied to the cooling block while the heater is cooled.

Abstract translation: 半导体制造装置可以包括：拾取单元，被配置为拾取半导体制造装置的第一区域中的芯片; 接合头，被配置为接收所拾取的芯片并且被配置为在所述半导体制造装置的第二区域中从所述第一区域移动到电路板的顶部; 和/或配置成在从第一区域移动到第二区域时检测电路板上的接合位置的光学单元。 半导体制造装置可以包括：接合头，包括用于加热芯片并将芯片接合到电路板上的加热器; 和/或与加热器相邻的冷却块，冷却液通过该冷却块流动。 当加热器产生热量时，冷却液体可从冷却块移除。 冷却液可以在加热器被冷却时供应到冷却块。

公开(公告)号：US20240183657A1

公开(公告)日：2024-06-06

申请号：US18527700

申请日：2023-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daisuke NAGATOMO ,  Shinji UEYAMA ,  Takamasa SUGIURA ,  Euisun CHOI ,  Fumitaka MOROISHI ,  Masanori IZUMITA ,  Takahiro TOKUMIYA ,  Tatsuya ISHIMOTO ,  Masato KAJINAMI

IPC: G01B11/30

CPC classification number: G01B11/303 ,  G01B11/306

Abstract: An optical device includes a monochromatic light source, a light distribution switching portion configured to transmit monochromatic light emitted from the monochromatic light source in one fan-shaped region among a plurality of fan-shaped regions centered on a central optical axis and block the monochromatic light in other fan-shaped regions, an objective lens, an aperture stop configured to collect reflected light from the object, an imaging lens, which has passed through the aperture stop, a light receiver on an imaging plane formed by the imaging lens and configured to receive the reflected light from the object and photoelectrically convert the received reflected light, and a controller configured to instruct the light distribution switching portion to change a region transmitting light over time, and calculate a normal direction of the object based on an electrical signal photoelectrically converted by the light receiver.

公开(公告)号：US20200209164A1

公开(公告)日：2020-07-02

申请号：US16678226

申请日：2019-11-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shinji UEYAMA ,  Fumitaka MOROISHI ,  Masato KAJINAMI

IPC: G01N21/95 ,  H01L21/68 ,  G03F9/00

Abstract: A method for adjusting inclination between wafers may include providing a first infrared light onto a first grid pattern in a first region in a first wafer and a second grid pattern in a second wafer, the first and second grid patterns overlapping, calculating a first distance in the first region between the first and second wafers based on a first Moiré pattern from the overlapping first and second grid patterns, providing a second infrared light onto a third grid pattern in a second region in the first wafer and a fourth grid pattern in the second wafer, the third and fourth grid patterns overlapping, calculating a second distance in the second region between the first and second wafers based on a second Moiré pattern from the overlapping third and fourth grid patterns, and adjusting relative inclination between the first and second wafers based on the first and second distances.

公开(公告)号：US20240186278A1

公开(公告)日：2024-06-06

申请号：US18457785

申请日：2023-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Masato KAJINAMI ,  Hansung CHO ,  Kazuya ONO ,  Byeongjin KIM ,  Daisuke NAGATOMO ,  Fumitaka MOROISHI ,  Masanori IZUMITA ,  Sungmin AHN

IPC: H01L23/00 ,  H01L21/67 ,  H01L21/68

CPC classification number: H01L24/74 ,  H01L21/67259 ,  H01L21/681 ,  H01L24/80 ,  H01L2224/74 ,  H01L2224/80895 ,  H01L2924/40

Abstract: Provided are mounting devices and mounting methods configured to realize high-precision mounting. A mounting device including a bonding actuator having a housing, a slider accommodated in the housing in a non-contact state and provided with a head, a coil and a yoke in a non-contact state, two voice coil motors (VCMs) driven in an X-axis direction, three VCMs driven in a Y-axis direction, and one VCM driven in a Z-axis direction may be provided. The coil may be fixed to the housing and the yoke may be fixed to the slider. The bonding actuator may perform bonding while adjusting a relative position and parallelism of a chip and a wafer, by driving the slider in six axial directions, which include the X-axis direction, the Y-axis direction, the Z-axis direction, a Tx direction, a Ty direction, and a Tz direction.

公开(公告)号：US20220157633A1

公开(公告)日：2022-05-19

申请号：US17385095

申请日：2021-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Masato KAJINAMI ,  Takamasa SUGIURA ,  Fumitaka MOROISHI

IPC: H01L21/68 ,  H01L21/683

Abstract: A wafer bonding apparatus may include a first chuck, a second chuck, and a pressure device. The first chuck may include a hole formed through a central portion of the first chuck. The second chuck may have a hole formed through a central portion of the second chuck. The pressure device may be configured to pressurize a wafer toward the second chuck through the holes. An air bearing may be interposed between the pressure device and the first chuck to suppress a dislocation of the pressure device.

公开(公告)号：US20220139755A1

公开(公告)日：2022-05-05

申请号：US17375263

申请日：2021-07-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Naoyuki TAKADA ,  Masato KAJINAMI ,  Tatsuya ISHIMOTO

IPC: H01L21/683

Abstract: A semiconductor manufacturing apparatus comprises an adsorption unit defining a plurality of pressing holes in the adsorption unit, the plurality of pressing holes configured to eject gas, and defining a plurality of suction holes in the adsorption unit, the plurality of suction holes configured to suction the gas and to handle a semiconductor chip through the gas. At least one of the suction holes is adjacent to at least one of an apex of the adsorption unit or an edge of the adsorption unit.

公开(公告)号：US20200217805A1

公开(公告)日：2020-07-09

申请号：US16583434

申请日：2019-09-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Takamasa SUGIURA ,  Fumitaka MOROISHI ,  Masato KAJINAMI

IPC: G01N21/95 ,  H01L21/687 ,  H01L21/67 ,  G01N21/64 ,  G01N21/88 ,  H04N5/235 ,  H04N5/225 ,  G06T7/00

Abstract: A wafer measurement apparatus for measuring a bonding strength of a bonded wafer includes a wafer holder to hold a bonded wafer into which a blade is inserted and where a crack occurs, a lighting assembly including a light source, a light source controller to select the light source of the lighting assembly for detection of the crack reflected in the bonded wafer, on photographing conditions, a photographing assembly to photograph the bonded wafer by using the photographing conditions corresponding to a wavelength of the light source, on sensitivity of the wavelength of the light source, and a calculator to select one photographing condition, transmit the selected photographing condition, and calculate bonding strength, on a crack distance from a blade edge, extracted from an image of the bonded wafer, to a crack edge.

公开(公告)号：US20150024551A1

公开(公告)日：2015-01-22

申请号：US14283238

申请日：2014-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoshiaki YUKIMORI ,  Shinji UEYAMA ,  Masato KAJINAMI

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L24/93 ,  H01L21/561 ,  H01L21/78 ,  H01L24/75 ,  H01L24/83 ,  H01L24/95 ,  H01L2224/83091 ,  H01L2224/83121 ,  H01L2224/83203

Abstract: A method of manufacturing a semiconductor device includes: providing a first substrate that includes internal wiring, the first substrate including an array of chip mounting regions that includes a first chip mounting region; placing the first substrate on a first carrier line; providing a first semiconductor chip; placing the first semiconductor chip on a first moveable tray; vertically aligning the first chip mounting region of the first substrate with the first semiconductor chip, and performing initial bonding of the first semiconductor chip to the first chip mounting region of the first substrate; and performing subsequent bonding on the initially-bonded first semiconductor chip and first mounting region of the first substrate, thereby more strongly bonding the first semiconductor chip to the first substrate at the first mounting region. The initial bonding occurs after performing a subsequent bonding of at least one other semiconductor chip on the first substrate.

Abstract translation: 一种制造半导体器件的方法包括：提供包括内部布线的第一基板，所述第一基板包括具有第一芯片安装区域的芯片安装区域阵列; 将第一衬底放置在第一载体线上; 提供第一半导体芯片; 将第一半导体芯片放置在第一可移动托盘上; 将第一基板的第一芯片安装区域与第一半导体芯片垂直对准，并且将第一半导体芯片初始接合到第一基板的第一芯片安装区域; 以及在所述第一基板的初始接合的第一半导体芯片和第一安装区域上进行后续的接合，从而在所述第一安装区域将所述第一半导体芯片与所述第一基板更牢固地接合。 在执行第一衬底上的至少一个其它半导体芯片的后续接合之后发生初始接合。

公开(公告)号：US20230369078A1

公开(公告)日：2023-11-16

申请号：US18105653

申请日：2023-02-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tatsuya ISHIMOTO ,  Fumitaka MOROISHI ,  Masato KAJINAMI

IPC: H01L21/67 ,  H01L21/683

CPC classification number: H01L21/67132 ,  H01L21/6838 ,  H01L21/67242

Abstract: A chip peeling apparatus is provided that includes a housing having a seating surface for mounting a wafer, a recessed portion and a first vacuum suction hole in the seating surface, and a second vacuum suction hole, a blow hole and a protrusion in the recessed portion. The chip peeling apparatus further includes: a vacuum suction source that evacuates the first vacuum suction hole and the second vacuum suction hole; a pressure detector that detects a degree of vacuum of the second vacuum suction hole; a pressurization source that sends a fluid to the blow hole; a flow rate control valve; and a controller that determines a flow rate of the fluid to be sent to the blow hole, based on the degree of vacuum, and controls, via the flow rate control valve, the fluid sent from the pressurization source to flow at the determined flow rate.

公开(公告)号：US20230178394A1

公开(公告)日：2023-06-08

申请号：US18062830

申请日：2022-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tatsuya ISHIMOTO ,  Naoyuki TAKADA ,  Takahiro TOKUMIYA ,  Masato KAJINAMI

IPC: H01L21/67

CPC classification number: H01L21/67132

Abstract: A chip peeling apparatus may include a peeling device. The peeling device may include a plurality of vacuum adsorption holes and a plurality of first air blow holes arranged around the plurality of vacuum adsorption holes. The peeling device may be configured to peel a chip off a tape when the peeling device is arranged below a region of the tape on which the chip is attached, vacuum pressure is applied through the plurality of vacuum adsorption holes to adsorb the peeling device to the region of the tape, and a first air blow is directed through the plurality of first air blow holes to the region of the tape.