公开(公告)号：US20230187548A1

公开(公告)日：2023-06-15

申请号：US17976955

申请日：2022-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： WONSOK LEE ,  MIN TAE RYU ,  SUNGWON YOO ,  KISEOK LEE ,  MIN HEE CHO

IPC: H01L29/78 ,  G11C5/06 ,  H01L29/08 ,  H01L29/10 ,  H01L27/105

CPC classification number: H01L29/7827 ,  G11C5/063 ,  H01L27/1052 ,  H01L29/0847 ,  H01L29/1033

Abstract: A semiconductor memory device includes bit lines disposed on a substrate and extending in a first direction in parallel to each other, a hydrogen supply insulating layer including hydrogen and filling a space between the bit lines, a source pattern located on each of the bit lines and being in partial contact with the hydrogen supply insulating layer, a hydrogen diffusion barrier layer covering a top surface of the hydrogen supply insulating layer and being in contact with a side surface of the source pattern, a first channel pattern located on the source pattern, a first word line being adjacent to a side surface of the first channel pattern and crossing over the bit lines, and a landing pad on the first channel pattern.

公开(公告)号：US20210193661A1

公开(公告)日：2021-06-24

申请号：US17032040

申请日：2020-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： KYUNGHWAN LEE ,  YONGSEOK KIM ,  HYUNCHEOL KIM ,  SATORU YAMADA ,  SUNGWON YOO ,  JAEHO HONG

IPC: H01L27/108 ,  G11C7/18

Abstract: Memory devices may include a source region, channels, a gate insulation layer pattern, a selection gate pattern, a first gate pattern, a second gate pattern and a drain region. The source region may include first impurities having a first conductivity type at an upper portion of a substrate. The channels may contact the source region. Each of the channels may extend in a vertical direction that is perpendicular to an upper surface of the substrate. The selection gate pattern may be on sidewalls of the channels. The first gate pattern may be on the sidewalls of the channels. The first gate pattern may be a common electrode of all of multiple channels. The second gate patterns may be on the sidewalls of the channels. The drain region may include second impurities having a second conductivity type that is different from the first conductivity type at an upper portion of each of the channels.

公开(公告)号：US20220367514A1

公开(公告)日：2022-11-17

申请号：US17671533

申请日：2022-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUNCHEOL KIM ,  YONGSEOK KIM ,  DONGSOO WOO ,  SUNGWON YOO ,  KYUNGHWAN LEE ,  JAEHO HONG

IPC: H01L27/11597 ,  H01L27/11587

Abstract: A semiconductor memory device may include a stack including word lines and interlayer insulating patterns alternatingly stacked on a substrate, the word lines being extended in a first direction parallel to a top surface of the substrate, semiconductor patterns crossing the word lines and having a long axis extended in a second direction parallel to the top surface of the substrate, data storage patterns respectively interposed between the semiconductor patterns and the word lines, the data storage patterns including a ferroelectric material, bit lines extended in a third direction perpendicular to the top surface of the substrate and spaced apart from each other in the first direction, each of the bit lines being in contact with first side surfaces of the semiconductor patterns spaced apart from each other in the third direction, and a source line in contact with second side surfaces of the semiconductor patterns.

公开(公告)号：US20230337413A1

公开(公告)日：2023-10-19

申请号：US17981719

申请日：2022-11-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： MIN HEE CHO ,  MIN TAE RYU ,  Huije Ryu ,  SUNGWON YOO ,  Yongjin Lee ,  WONSOK LEE

IPC: H01L27/108 ,  G11C5/06

CPC classification number: H01L27/10814 ,  G11C5/063 ,  H01L27/10897 ,  H01L27/10888 ,  H01L27/10873 ,  H01L27/10885 ,  H01L27/10891

Abstract: Disclosed are semiconductor memory devices and their fabrication methods. The semiconductor memory device comprises a peripheral circuit structure including peripheral circuits on a semiconductor substrate and a first dielectric layer on the peripheral circuits, a cell array structure on the semiconductor substrate, and a shield layer between the peripheral circuit structure and the cell array structure. The cell array structure includes bit lines, first and second active patterns on the bit lines, first word lines that extend in a second direction on the first active patterns, second word lines that extend in the second direction on the second active patterns, data storage patterns on the first and second active patterns, and a second dielectric layer on the semiconductor substrate. A hydrogen concentration of the first dielectric layer is greater than that of the second dielectric layer.

公开(公告)号：US20220130856A1

公开(公告)日：2022-04-28

申请号：US17335763

申请日：2021-06-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUNCHEOL KIM ,  JAEHO HONG ,  YONGSEOK KIM ,  ILGWEON KIM ,  HYEOUNGWON SEO ,  SUNGWON YOO ,  KYUNGHWAN LEE

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L25/065 ,  G11C7/18 ,  G11C8/14

Abstract: A semiconductor memory device includes first conductive lines stacked in a first direction perpendicular to a top surface of a substrate, second conductive lines extending in the first direction and intersecting the first conductive lines, and memory cells provided at intersection points between the first conductive lines and the second conductive lines, respectively. Each of the memory cells includes a semiconductor pattern parallel to the top surface of the substrate, the semiconductor pattern including a source region having a first conductivity type, a drain region having a second conductivity type, and a channel region between the source region and the drain region, first and second gate electrodes surrounding the channel region of the semiconductor pattern, and a charge storage pattern between the semiconductor pattern and the first and second gate electrodes.