公开(公告)号：US20250014670A1

公开(公告)日：2025-01-09

申请号：US18399872

申请日：2023-12-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Won Park ,  Kuihan Ko ,  Heewon Son

IPC: G11C29/52 ,  G11C16/08 ,  G11C16/16

Abstract: A non-volatile integrated circuit memory device includes a first memory block having first and second memory sub-blocks therein, and a second memory block having third and fourth memory sub-blocks therein. A sub-block manager is also provided, which is configured to: (i) determine whether the second memory sub-block is a reclaim sub-block when the first memory sub-block has an uncorrectable error (UECC) therein, and (ii) reclaim the first and second memory sub-blocks to the third and fourth memory sub-blocks, respectively, in response to determining that the second memory sub-block is a reclaim sub-block.

公开(公告)号：US20240087658A1

公开(公告)日：2024-03-14

申请号：US18304773

申请日：2023-04-21

Applicant: Samsung Electronics Co., Ltd

Inventor： Kuihan KO ,  Sang-Won Park

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/16

CPC classification number: G11C16/3445 ,  G11C16/0433 ,  G11C16/16

Abstract: Disclosed is a storage device which includes a first word line connected with memory cells being in a program state, a second word line connected with memory cells being an erase state, and a free word line between the first and second word lines and connected with memory cells being the erase state. Whether a block continuous-write is possible with respect to the memory cells connected with the second word line is determined by verifying the erase state of the memory cells connected with the free word line during one busy signal period. According to the present disclosure, because whether a block continuous-write is possible is determined with respect to a plurality of free pages during one busy signal period, a time taken to perform the block continuous-write operation may decrease.

公开(公告)号：US12176046B2

公开(公告)日：2024-12-24

申请号：US17955858

申请日：2022-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yohan Lee ,  Sang-Wan Nam ,  Sang-Won Park ,  Jiho Cho ,  Eunhyang Park

IPC: G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/34

Abstract: Disclosed is an operation method of a memory device that includes a plurality of memory cells stacked in a direction perpendicular to a substrate. The method includes performing first to (n−1)-th program loops on selected memory cells connected to a selected word line from among the plurality of memory cells, based on a first program parameter, and after the (n−1)-th program loop is performed, performing n-th to k-th program loops on the selected memory cells, based on a second program parameter different from the first program parameter. Herein, n is an integer greater than 1 and k is an integer greater than or equal to n. The first and second program parameters include information about at least two of a program voltage increment, a 2-step verify range, and a bit line forcing voltage used in the first to k-th program loops.

公开(公告)号：US11495541B2

公开(公告)日：2022-11-08

申请号：US16592886

申请日：2019-10-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bongsoon Lim ,  Sang-Wan Nam ,  Sang-Won Park ,  Sang-Won Shim ,  Hongsoo Jeon ,  Yonghyuk Choi

IPC: H01L23/535 ,  H01L27/11573 ,  H01L27/11582

Abstract: A three-dimensional semiconductor memory device may include a first stack structure block including first stack structures arranged in a first direction on a substrate, a second stack structure block including second stack structures arranged in the first direction on the substrate, a separation structure disposed on the substrate between the first and second stack structure blocks and including first mold layers and second mold layers, and a contact plug penetrating the separation structure. A bottom surface of the contact plug may contact the substrate.

公开(公告)号：US11322205B2

公开(公告)日：2022-05-03

申请号：US16823275

申请日：2020-03-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Won Park ,  Sang-Wan Nam ,  Ji Yeon Shin ,  Won Bo Shim ,  Jung-Yun Yun ,  Ji Ho Cho ,  Sang Gi Hong

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/24 ,  G11C16/08 ,  H01L27/11582 ,  H01L27/11556

Abstract: A method for programming a non-volatile memory device is provided. The method comprises applying a program word line voltage with a voltage level changed stepwise to a selected word line connected to a plurality of memory cells, and applying a program bit line voltage to a first bit line of a plurality of bit lines connected to a plurality of first memory cells, while the program word line voltage is applied to the selected word line. The program bit line voltage transitions from a first voltage level to one of a program inhibit voltage level, a program voltage level, and a second voltage level. The first and second voltage levels are between the program inhibit voltage level and program voltage level.

公开(公告)号：US10804293B2

公开(公告)日：2020-10-13

申请号：US16440299

申请日：2019-06-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Won Park ,  Sang-Wan Nam ,  Bong-Soon Lim

IPC: H01L27/11582 ,  G11C16/04 ,  G11C16/14 ,  G11C16/10 ,  G11C16/26 ,  H01L27/11573 ,  G06F3/06 ,  H01L27/1157 ,  H01L27/11565

Abstract: A nonvolatile memory device includes a semiconductor substrate including a page buffer region, a memory cell array, bitlines, first vertical conduction paths, and second vertical conduction paths. The memory cell array is formed in a memory cell region above the semiconductor substrate and includes memory cells. The bitlines extend in a column direction above the memory cell array. Each of bitlines is cut into each of first bitline segments and each of second bitline segments. The first vertical conduction paths extend in a vertical direction and penetrate a column-directional central region of the memory cell region. The first vertical conduction paths connect the first bitline segments and the page buffer region. The second vertical conduction paths extend in the vertical direction and penetrate the column-directional central region. The second vertical conduction paths connect the second bitline segments and the page buffer region.

公开(公告)号：US10388367B2

公开(公告)日：2019-08-20

申请号：US15351552

申请日：2016-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Won Park ,  Dongkyo Shim ,  Kitae Park ,  Sang-Won Shim

IPC: G11C8/08 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  G11C16/34 ,  G11C29/02

Abstract: A nonvolatile memory device includes a voltage generator that sequentially provides a first setup voltage and second setup voltage to a word line of a memory cell array, and control logic including a time control unit that determines a word line setup time for the word line in relation to the second setup voltage based on a difference between the first and second setup voltages.

公开(公告)号：US12002514B2

公开(公告)日：2024-06-04

申请号：US17706097

申请日：2022-03-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Won Park ,  Won-Taeck Jung ,  Han-Jun Lee ,  Su Chang Jeon

IPC: G11C8/12 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/3459 ,  G11C8/12

Abstract: A nonvolatile memory may include; a first memory cell array including a first selection transistor connected to a first string selection line, a second memory cell array including a second selection transistor connected to a second string selection line and spaced apart from the first string selection line by a first cutting line, and a peripheral circuit. The peripheral circuit may provide a first program voltage to the first selection transistor, provide a second program voltage to the second selection transistor different from the first program voltage, program the first selection transistor with a first threshold voltage in response to the first program voltage, and program the second selection transistor with a second threshold voltage level greater than the first threshold voltage in response to the second program voltage.

公开(公告)号：US11367487B2

公开(公告)日：2022-06-21

申请号：US16693925

申请日：2019-11-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Won Park ,  Won Bo Shim ,  Bong Soon Lim

IPC: G11C16/16 ,  G11C16/24 ,  G11C16/34 ,  G11C16/12

Abstract: A non-volatile memory device includes a memory cell array including a plurality of cell strings, each of the plurality of cell strings includes a gate-induced drain leakage (GIDL) transistor and a memory cell group, and a control logic to apply a voltage to each of the plurality of cell strings. The control logic performs a first erase operation of erasing the memory cell groups of each of the plurality of cell strings, a first verification operation of detecting erase results of the memory cell groups of each of the plurality of cell strings, and a program operation of programming the GIDL transistors of some of the plurality of cell strings.

公开(公告)号：US11062775B2

公开(公告)日：2021-07-13

申请号：US16846539

申请日：2020-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bongsoon Lim ,  Jung-Yun Yun ,  Ji-Suk Kim ,  Sang-Won Park

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/26 ,  G11C16/08

Abstract: A storage device includes a nonvolatile memory device and a controller. The controller provides the nonvolatile memory device with first data, an address, and a program start command and provides the nonvolatile memory device with second data after the program start command is provided the nonvolatile memory device. The nonvolatile memory device is configured to initiate a program operation, which is based on the first data, in response to the program start command and to continue to perform, based on the first data and the second data, the program operation when the second data is provided to the nonvolatile memory device. The nonvolatile memory device is configured to perform a program and a verification read of a first program loop based on the first data, the verification read of the first program loop being performed using one verification voltage.