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公开(公告)号：US09189174B2
公开(公告)日：2015-11-17
申请号：US13904047
申请日：2013-05-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Han-Jun Lee , Dae-Seok Byeon
CPC classification number: G06F3/0679 , G06F3/061 , G06F3/0638 , G11C5/145 , G11C16/12 , G11C16/30
Abstract: Provided are a nonvolatile memory device and a method for operating the nonvolatile memory device. The method for operating the nonvolatile memory device includes generating a first program voltage, applying the generated first program voltage to a first word line to which a first memory cell is connected for performing a first program operation on the first memory cell, determining whether a number of pulses of a pumping clock signal for generating the first program voltage is greater than or equal to a predetermined critical value n (where n is a natural number), and stopping the performing of the first program operation on the first memory cell when the number of pulses of the pumping clock signal is determined to be greater than or equal to the predetermined critical value n.
Abstract translation: 提供了一种用于操作非易失性存储器件的非易失性存储器件和方法。 用于操作非易失性存储器件的方法包括产生第一编程电压，将产生的第一编程电压施加到连接有第一存储单元的第一字线用于对第一存储器单元执行第一程序操作，确定数字 用于产生第一编程电压的泵浦时钟信号的脉冲大于或等于预定临界值n（其中n是自然数），并且当数量为第一存储器单元的数量时停止执行第一程序操作 泵浦时钟信号的脉冲被确定为大于或等于预定临界值n。
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Patent Agency Ranking
公开(公告)号：US12002514B2
公开(公告)日：2024-06-04
申请号：US17706097
申请日：2022-03-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sang-Won Park , Won-Taeck Jung , Han-Jun Lee , Su Chang Jeon
CPC classification number: G11C16/10 , G11C16/0483 , G11C16/3459 , G11C8/12
Abstract: A nonvolatile memory may include; a first memory cell array including a first selection transistor connected to a first string selection line, a second memory cell array including a second selection transistor connected to a second string selection line and spaced apart from the first string selection line by a first cutting line, and a peripheral circuit. The peripheral circuit may provide a first program voltage to the first selection transistor, provide a second program voltage to the second selection transistor different from the first program voltage, program the first selection transistor with a first threshold voltage in response to the first program voltage, and program the second selection transistor with a second threshold voltage level greater than the first threshold voltage in response to the second program voltage.
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公开(公告)号：US08705284B2
公开(公告)日：2014-04-22
申请号：US13891657
申请日：2013-05-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Moo Sung Kim , Han-Jun Lee
IPC: G11C16/04
CPC classification number: G11C16/10 , G11C16/3404
Abstract: A flash memory device includes a memory cell array made up of memory cells arranged in rows and columns. A first page of data is programmed in selected memory cells of the memory cell array, and a second page of data is subsequently programmed in the selected memory cells. The first page of data is programmed using a program voltage having a first start value, and the second page of data is programmed using a program voltage having a second start value determined by a programming characteristic of the selected memory cells.
Abstract translation: 闪速存储器件包括由以行和列排列的存储单元组成的存储单元阵列。 数据的第一页被编程在存储单元阵列的选定的存储单元中，随后在所选存储单元中编程第二页数据。 使用具有第一起始值的编程电压对数据的第一页进行编程，并且使用具有由所选存储单元的编程特性确定的第二起始值的编程电压对第二数据页进行编程。
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公开(公告)号：US11776642B2
公开(公告)日：2023-10-03
申请号：US17548774
申请日：2021-12-13
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sung-Won Yun , Han-Jun Lee
CPC classification number: G11C16/349 , G11C11/5628 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/3404 , G11C16/3459 , G11C29/021 , G11C29/028 , G11C16/0483
Abstract: A method of operating a memory device that includes a plurality of stages each having a plurality of page buffers. The method including performing a verify operation of a first program loop from among a plurality of program loops, the verify operation of the first program loop including, performing a first off-cell counting operation on a first stage of the plurality of stages based on a first sampling rate to generate a first off-cell counting result; selectively changing the first sampling rate based on the first off-cell counting result to generate a changed first sampling rate; and performing a second off-cell counting operation on a second stage of the plurality of stages based on one of the first sampling rate and the changed first sampling rate to generate a second off-cell counting result.
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公开(公告)号：US10734082B2
公开(公告)日：2020-08-04
申请号：US16275108
申请日：2019-02-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Han-Jun Lee , Seung-Bum Kim , Chul-Bum Kim , Seung-Jae Lee
IPC: G11C16/28 , G11C16/34 , G11C16/16 , G11C8/14 , G11C16/24 , G11C7/18 , G11C16/08 , G11C29/08 , G11C7/04
Abstract: A memory device includes multiple word lines. A method of operating the memory device includes: performing a first dummy read operation, with respect to first memory cells connected to a first word line among the word lines, by applying a dummy read voltage, having an offset level of a first level, to the first word line; determining, based on a result of the performing of the first dummy read operation, degradation of a threshold voltage distribution of the first memory cells; adjusting an offset level of the dummy read voltage as a second level, based on a result of the determining of the threshold voltage distribution; and performing a second dummy read operation with respect to second memory cells connected to a second word line among the word lines, by applying a dummy read voltage, having the offset level adjusted as the second level, to the second word line among the word lines.
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公开(公告)号：US11049547B1
公开(公告)日：2021-06-29
申请号：US16986019
申请日：2020-08-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Han-Jun Lee , Seung-Bum Kim , Chul-Bum Kim , Seung-Jae Lee
IPC: G11C11/408 , G11C11/4099 , G11C11/4093 , G11C11/4074 , G11C5/02 , G11C29/02 , G11C29/50
Abstract: A memory device includes multiple word lines. A method of operating the memory device includes: performing a first dummy read operation, with respect to first memory cells connected to a first word line among the word lines, by applying a dummy read voltage, having an offset level of a first level, to the first word line; determining, based on a result of the performing of the first dummy read operation, degradation of a threshold voltage distribution of the first memory cells; adjusting an offset level of the dummy read voltage as a second level, based on a result of the determining of the threshold voltage distribution; and performing a second dummy read operation with respect to second memory cells connected to a second word line among the word lines, by applying a dummy read voltage, having the offset level adjusted as the second level, to the second word line among the word lines.
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