公开(公告)号：US10074717B2

公开(公告)日：2018-09-11

申请号：US14993212

申请日：2016-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Han Lee ,  Jae-Hwan Lee ,  Sang-Su Kim ,  Hwan-Wook Choi ,  Tae-Jong Lee ,  Seung-Mo Ha

IPC: H01L29/49 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/0657 ,  H01L21/823431 ,  H01L21/823468 ,  H01L27/0886

Abstract: A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.

公开(公告)号：US20190019864A1

公开(公告)日：2019-01-17

申请号：US16124521

申请日：2018-09-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Han Lee ,  Jae-Hwan Lee ,  Sang-Su Kim ,  Hwan-Wook Choi ,  Tae-Jong Lee ,  Seung-Mo Ha

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088

Abstract: A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.

公开(公告)号：US11515390B2

公开(公告)日：2022-11-29

申请号：US16993514

申请日：2020-08-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Han Lee ,  Jae-Hwan Lee ,  Sang-Su Kim ,  Hwan-Wook Choi ,  Tae-Jong Lee ,  Seung-Mo Ha

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/8234

Abstract: A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.

公开(公告)号：US09972538B2

公开(公告)日：2018-05-15

申请号：US15196870

申请日：2016-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheol Kim ,  Dong-Hoon Khang ,  Do-Hyoung Kim ,  Seung-Jin Mun ,  Yong-Joon Choi ,  Seung-Mo Ha

IPC: H01L21/311 ,  H01L21/8234 ,  H01L21/027 ,  H01L21/02 ,  H01L21/3115 ,  H01L21/3105 ,  H01L21/033 ,  H01L21/308 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/02115 ,  H01L21/02271 ,  H01L21/02321 ,  H01L21/02323 ,  H01L21/0234 ,  H01L21/0273 ,  H01L21/0275 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/31155 ,  H01L29/66795

Abstract: Methods for fabricating a semiconductor device include forming a composite film, forming a rough pattern on the composite film, forming a smooth pattern by subjecting the rough pattern to ion implantation and a plasma treatment, and patterning the composite film using the smooth pattern as a first mask.

公开(公告)号：US11610966B2

公开(公告)日：2023-03-21

申请号：US16694031

申请日：2019-11-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Han Lee ,  Jae-Hwan Lee ,  Sang-Su Kim ,  Hwan-Wook Choi ,  Tae-Jong Lee ,  Seung-Mo Ha

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/8234

Abstract: A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.

公开(公告)号：US09985025B1

公开(公告)日：2018-05-29

申请号：US15496145

申请日：2017-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-Il Kim ,  Seung-Jin Mun ,  Kwang-Yong Yang ,  Young-Mook Oh ,  Ah-Young Cheon ,  Seung-Mo Ha

IPC: H01L29/00 ,  H01L21/311 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  B82Y10/00 ,  H01L21/3086 ,  H01L21/762 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/775

Abstract: An active pattern structure may include a substrate including an active pattern array defined by a plurality of trenches including first to third trenches, and first to third isolation patterns in the first to third trenches, respectively. The active pattern array may include a plurality of first and second active patterns extending in a first direction, and the first to third trenches may be between the first and second active patterns and may include different widths from each other. The active pattern array may include an active pattern group including one of the first active patterns and one of the second active patterns sequentially arranged in a second direction substantially perpendicular to the first direction. Each of the first and second active patterns may have a minute width.