公开(公告)号：US10446561B2

公开(公告)日：2019-10-15

申请号：US16115711

申请日：2018-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Jine Park ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Bo-Un Yoon ,  Keun-Hee Bai ,  Kwang-Yong Yang ,  Kyoung-Hwan Yeo ,  Yong-Ho Jeon

IPC: H01L27/11 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78 ,  H01L21/762

Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

公开(公告)号：US20180374859A1

公开(公告)日：2018-12-27

申请号：US16115711

申请日：2018-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Jine Park ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Bo-Un Yoon ,  Keun-Hee Bai ,  Kwang-Yong Yang ,  Kyoung-Hwan Yeo ,  Yong-Ho Jeon

IPC: H01L27/11 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/78 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/06

CPC classification number: H01L27/1104 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1116 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848

Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

公开(公告)号：US10096605B2

公开(公告)日：2018-10-09

申请号：US15680960

申请日：2017-08-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Jine Park ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Bo-Un Yoon ,  Keun-Hee Bai ,  Kwang-Yong Yang ,  Kyoung-Hwan Yeo ,  Yong-Ho Jeon

IPC: H01L29/06 ,  H01L27/11 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L21/762

Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

公开(公告)号：US09985025B1

公开(公告)日：2018-05-29

申请号：US15496145

申请日：2017-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-Il Kim ,  Seung-Jin Mun ,  Kwang-Yong Yang ,  Young-Mook Oh ,  Ah-Young Cheon ,  Seung-Mo Ha

IPC: H01L29/00 ,  H01L21/311 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  B82Y10/00 ,  H01L21/3086 ,  H01L21/762 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/775

Abstract: An active pattern structure may include a substrate including an active pattern array defined by a plurality of trenches including first to third trenches, and first to third isolation patterns in the first to third trenches, respectively. The active pattern array may include a plurality of first and second active patterns extending in a first direction, and the first to third trenches may be between the first and second active patterns and may include different widths from each other. The active pattern array may include an active pattern group including one of the first active patterns and one of the second active patterns sequentially arranged in a second direction substantially perpendicular to the first direction. Each of the first and second active patterns may have a minute width.

公开(公告)号：US09954061B2

公开(公告)日：2018-04-24

申请号：US15605698

申请日：2017-05-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongyun Lee ,  Kwang-Yong Yang ,  Keomyoung Shin ,  Jinwook Lee ,  Yongseok Lee

IPC: H01L27/088 ,  H01L29/10 ,  H01L29/06 ,  H01L29/423 ,  H01L29/40 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/1033 ,  H01L21/823412 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/6656

Abstract: A semiconductor device includes an isolation pattern on a substrate, the isolation pattern having a lower insulating pattern on the substrate, and a spacer to cover side surfaces of the lower insulating pattern, a vertical structure through the isolation pattern to contact the substrate, the vertical structure having a first semiconductor layer on the substrate, a lower end of the first semiconductor layer being at a lower level than a lower surface of the isolation pattern, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer, and a gate electrode crossing the vertical structure and extending over the isolation pattern.

公开(公告)号：US10593596B2

公开(公告)日：2020-03-17

申请号：US15959319

申请日：2018-04-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongwoo Han ,  Kwang-Yong Yang ,  Jinwook Lee ,  Kyungyub Jeon ,  Haegeon Jung ,  Dohyoung Kim

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L21/306

Abstract: A method of fabricating a semiconductor device includes forming first and second active patterns on first and second regions, respectively, of a substrate, forming first and second gate structures on the first and second active patterns, respectively, forming a coating layer to cover the first and second gate structures and the first and second active patterns, and forming a first recess region in the first active pattern between the first gate structures and a second recess region in the second active pattern between the second gate structures.

公开(公告)号：US09984931B2

公开(公告)日：2018-05-29

申请号：US15260952

申请日：2016-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongwoo Han ,  Kwang-Yong Yang ,  Jinwook Lee ,  Kyungyub Jeon ,  Haegeon Jung ,  Dohyoung Kim

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L21/306

CPC classification number: H01L21/823431 ,  H01L21/30604 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/6656 ,  H01L29/66795

Abstract: A method of fabricating a semiconductor device includes forming first and second active patterns on first and second regions, respectively, of a substrate, forming first and second gate structures on the first and second active patterns, respectively, forming a coating layer to cover the first and second gate structures and the first and second active patterns, and forming a first recess region in the first active pattern between the first gate structures and a second recess region in the second active pattern between the second gate structures.

公开(公告)号：US09941174B2

公开(公告)日：2018-04-10

申请号：US15007711

申请日：2016-01-27

Applicant: Samsung Electronics Co., Ltd

Inventor： Kyungin Choi ,  Ah-Young Cheon ,  Kwang-Yong Yang ,  Myungil Kang ,  Dohyoung Kim ,  YoonHae Kim

IPC: H01L31/0312 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L21/265 ,  H01L29/165

CPC classification number: H01L21/823814 ,  H01L21/26586 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/66545

Abstract: Semiconductor devices are providing including a first isolation region configured to define a first fin active region protruding from a substrate, first gate patterns on the first fin active region, and a first epitaxial region in the first fin active region between the first gate patterns. Sidewalls of the first epitaxial region have first inflection points so that an upper width of the first epitaxial region is greater than a lower width of the first epitaxial region.

公开(公告)号：US20170345825A1

公开(公告)日：2017-11-30

申请号：US15680960

申请日：2017-08-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Jine Park ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Bo-Un Yoon ,  Keun-Hee Bai ,  Kwang-Yong Yang ,  Kyoung-Hwan Yeo ,  Yong-Ho Jeon

IPC: H01L27/11 ,  H01L29/165 ,  H01L29/161 ,  H01L29/16 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/762 ,  H01L27/092 ,  H01L27/088 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L27/1104 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1116 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848

Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

公开(公告)号：US10312153B2

公开(公告)日：2019-06-04

申请号：US15914125

申请日：2018-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungin Choi ,  Ah-Young Cheon ,  Kwang-Yong Yang ,  Myungil Kang ,  Dohyoung Kim ,  YoonHae Kim

IPC: H01L29/66 ,  H01L21/265 ,  H01L27/092 ,  H01L29/165 ,  H01L21/8238

Abstract: Semiconductor devices are providing including a first isolation region configured to define a first fin active region protruding from a substrate, first gate patterns on the first fin active region, and a first epitaxial region in the first fin active region between the first gate patterns. Sidewalls of the first epitaxial region have first inflection points so that an upper width of the first epitaxial region is greater than a lower width of the first epitaxial region.