中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

17 records (took 0.017 seconds)

    Semiconductor device including stack structure with flat region
    1.
    发明授权
    Semiconductor device including stack structure with flat region 有权

    公开(公告)号：US11616021B2

    公开(公告)日：2023-03-28

    申请号：US17021321

    申请日：2020-09-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seungjun Shin ,  Siwan Kim ,  Bonghyun Choi

    IPC: H01L23/528 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11573 ,  H01L23/522 ,  H01L27/11582

    Abstract: A semiconductor device includes a lower structure, a stack structure on the lower structure and extending from a memory cell region into a connection region, gate contact plugs on the stack structure in the connection region, and a memory vertical structure through the stack structure in the memory cell region, wherein the stack structure includes interlayer insulating layers and horizontal layers alternately stacked, wherein, in the connection region, the stack structure includes a staircase region and a flat region, wherein the staircase region includes lowered pads, wherein the flat region includes a flat pad region, a flat edge region, and a flat dummy region between the flat pad region and the flat edge region, and wherein the gate contact plugs include first gate contact plugs on the pads, flat contact plugs on the flat pad region, and a flat edge contact plug on the flat edge region.

    Vertical memory devices
    3.
    发明授权
    Vertical memory devices 有权

    公开(公告)号：US11430732B2

    公开(公告)日：2022-08-30

    申请号：US17027989

    申请日：2020-09-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seungjun Shin

    IPC: H01L23/528 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  H01L21/768 ,  H01L23/535 ,  H01L23/522

    Abstract: A vertical memory device includes a cell stacked structure, a wiring connection structure, and a first insulating interlayer. The cell stacked structure may include insulation layers and gate patterns repeatedly and alternately stacked on a first region of a substrate. The wiring connection structure may contact side walls of the cell stacked structure. The wiring connection structure may include a first staircase structure having one side of a stepped shape, a second staircase structure having one side of a stepped shape and disposed below the first staircase structure, and a first dummy staircase structure between the first and second staircase structures. The first and second staircase structures may be spaced apart from each other in the first direction, and both sides in the first direction of the first dummy staircase structure may have stepped shapes. The first insulating interlayer may be on the substrate to cover the wiring connection structure.

    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES
    4.
    发明申请
    THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES 有权

    公开(公告)号：US20210242236A1

    公开(公告)日：2021-08-05

    申请号：US17036997

    申请日：2020-09-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seungjun Shin ,  Siwan Kim ,  Bonghyun Choi

    IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11556 ,  H01L23/522

    Abstract: A three-dimensional (3D) semiconductor memory device includes electrode structures including a plurality of electrodes stacked on a semiconductor substrate, and the electrode structures extend in a first direction and are spaced apart from each other by separation regions in a second direction perpendicular to the first direction. The 3D semiconductor memory device includes ground select gate electrodes comprising lowermost electrodes among the plurality of electrodes of the electrode structures, wherein on a level of the ground select gate electrodes, the separation regions include a first end portion, and at least one ground select gate cutting region overlaps the first end portion of the separation regions and electrically isolates the ground select gate electrodes from each other.

    Memory device and clock training method thereof
    7.
    发明授权
    Memory device and clock training method thereof 有权

    公开(公告)号：US10304547B2

    公开(公告)日：2019-05-28

    申请号：US15700324

    申请日：2017-09-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yeonkyu Choi ,  Seungjun Shin

    IPC: H01L27/115 ,  G11C16/32 ,  G11C7/22 ,  G11C29/02

    Abstract: A training method for a memory device includes providing, at a memory controller, a clock signal to the memory device to synchronize a control signal at a reference time point of the clock signal. When the clock signal, such as a training clock signal, does not transition after the reference time point, a failure time point is found at which the memory device fails to sample the control signal at the reference time point, based on the clock signal and the control signal. A synchronization time point of the control signal may be set, at which the memory device secures a sampling margin for sampling the control signal at the reference time point, based on the failure time point. A sampler circuit may sample the control signal at an edge of a rising edge of the clock signal.

    MEMORY DEVICE
    9.
    发明公开
    MEMORY DEVICE 审中-公开

    公开(公告)号：US20240103735A1

    公开(公告)日：2024-03-28

    申请号：US18333690

    申请日：2023-06-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seungjun Shin ,  Yeongwoo Kang ,  DongHyeok Cho ,  Younghun Seo

    IPC: G06F3/06

    CPC classification number: G06F3/0614 ,  G06F3/0659 ,  G06F3/0673

    Abstract: Disclosed is a memory device which includes a first memory cell that is electrically connected with a first word line and a first bit line, a first bit line sense amplifier circuit that is electrically connected with the first bit line, a first local sense amplifier circuit that is electrically connected with the first bit line sense amplifier circuit through a first local input/output line, a first local driver that is electrically connected with the first local sense amplifier circuit through a first pre-global input/output line, and a sense amplifier and write driver that is electrically connected with the first local driver through a global input/output line, and the first local driver selectively electrical-disconnects the first pre-global input/output line from the global input/output line, based on an operation for the first memory cell.

    Vertical memory devices
    10.
    发明授权
    Vertical memory devices 有权

    公开(公告)号：US11894301B2

    公开(公告)日：2024-02-06

    申请号：US17895205

    申请日：2022-08-25

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seungjun Shin

    IPC: H01L23/528 ,  H01L21/768 ,  H01L23/535 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

    CPC classification number: H01L23/5283 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/535 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

    Abstract: A vertical memory device includes a cell stacked structure, a wiring connection structure, and a first insulating interlayer. The cell stacked structure may include insulation layers and gate patterns repeatedly and alternately stacked on a first region of a substrate. The wiring connection structure may contact side walls of the cell stacked structure. The wiring connection structure may include a first staircase structure having one side of a stepped shape, a second staircase structure having one side of a stepped shape and disposed below the first staircase structure, and a first dummy staircase structure between the first and second staircase structures. The first and second staircase structures may be spaced apart from each other in the first direction, and both sides in the first direction of the first dummy staircase structure may have stepped shapes. The first insulating interlayer may be on the substrate to cover the wiring connection structure.

Patent Agency Ranking