公开(公告)号：US20160064277A1

公开(公告)日：2016-03-03

申请号：US14674332

申请日：2015-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun PARK ,  Dong-Hyun Im ,  Soon-Gun Lee ,  Jong-Myeong Lee ,  Han-Jin Lim

IPC: H01L21/768 ,  H01L49/02

CPC classification number: H01L21/76837 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/02645 ,  H01L21/02653 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76844 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76889 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10855 ,  H01L28/91 ,  H01L29/413 ,  H01L2221/1094

Abstract: Methods of fabricating a semiconductor device may include forming guide patterns exposing base patterns, forming first nanowires on the base patterns by performing a first nanowire growth process, forming a first molding insulating layer between the first nanowires, forming holes exposing surfaces of the base patterns by removing the nanowires, and forming first electrodes including a conductive material in the holes.

Abstract translation: 制造半导体器件的方法可以包括形成引导图案，其暴露基底图案，通过执行第一纳米线生长工艺在基底图案上形成第一纳米线，在第一纳米线之间形成第一模制绝缘层， 去除纳米线，并在孔中形成包括导电材料的第一电极。

公开(公告)号：US09543196B2

公开(公告)日：2017-01-10

申请号：US14674332

申请日：2015-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Park ,  Dong-Hyun Im ,  Soon-Gun Lee ,  Jong-Myeong Lee ,  Han-Jin Lim

IPC: H01L21/20 ,  H01L21/82 ,  H01L21/768 ,  B82Y10/00 ,  H01L21/02 ,  H01L27/108 ,  H01L49/02 ,  H01L29/41

CPC classification number: H01L21/76837 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/02645 ,  H01L21/02653 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76844 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76889 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10855 ,  H01L28/91 ,  H01L29/413 ,  H01L2221/1094

Abstract: Methods of fabricating a semiconductor device may include forming guide patterns exposing base patterns, forming first nanowires on the base patterns by performing a first nanowire growth process, forming a first molding insulating layer between the first nanowires, forming holes exposing surfaces of the base patterns by removing the nanowires, and forming first electrodes including a conductive material in the holes.

Abstract translation: 制造半导体器件的方法可以包括形成引导图案，其暴露基底图案，通过执行第一纳米线生长工艺在基底图案上形成第一纳米线，在第一纳米线之间形成第一模制绝缘层， 去除纳米线，并在孔中形成包括导电材料的第一电极。

公开(公告)号：US09455259B2

公开(公告)日：2016-09-27

申请号：US14716371

申请日：2015-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Han-Jin Lim ,  Youn-Soo Kim ,  Hyun Park ,  Soon-Gun Lee ,  Eun-Ae Cho ,  Chin-Moo Cho ,  Sung-Jin Kim ,  Seok-Woo Nam

IPC: H01L27/108 ,  H01L49/02

CPC classification number: H01L27/10814 ,  H01L28/75 ,  H01L28/91

Abstract: A semiconductor device includes a capacitor with reduced oxygen defects at an interface between a dielectric layer and an electrode of the capacitor. The semiconductor device includes a lower metal layer; a dielectric layer on the lower metal layer and containing a first metal; a sacrificial layer on the dielectric layer and containing a second metal; and an upper metal layer on the sacrificial layer. An electronegativity of the second metal in the sacrificial layer is greater than an electronegativity of the first metal in the dielectric layer.

Abstract translation: 半导体器件包括在电介质层和电容器的电极之间的界面处具有减少的氧缺陷的电容器。 半导体器件包括下金属层; 在下金属层上的介电层并含有第一金属; 在介电层上的牺牲层并含有第二金属; 和牺牲层上的上金属层。 牺牲层中的第二金属的电负性大于电介质层中第一金属的电负性。

公开(公告)号：US20160079247A1

公开(公告)日：2016-03-17

申请号：US14716371

申请日：2015-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Han-Jin Lim ,  Youn-Soo Kim ,  Hyun Park ,  Soon-Gun Lee ,  Eun-Ae Cho ,  Chin-Moo Cho ,  Sung-Jin Kim ,  Seok-Woo Nam

IPC: H01L27/108 ,  H01L49/02

CPC classification number: H01L27/10814 ,  H01L28/75 ,  H01L28/91

Abstract: A semiconductor device includes a capacitor with reduced oxygen defects at an interface between a dielectric layer and an electrode of the capacitor. The semiconductor device includes a lower metal layer; a dielectric layer on the lower metal layer and containing a first metal; a sacrificial layer on the dielectric layer and containing a second metal; and an upper metal layer on the sacrificial layer. An electronegativity of the second metal in the sacrificial layer is greater than an electronegativity of the first metal in the dielectric layer.

Abstract translation: 半导体器件包括在电介质层和电容器的电极之间的界面处具有减少的氧缺陷的电容器。 半导体器件包括下金属层; 在下金属层上的介电层并含有第一金属; 在介电层上的牺牲层并含有第二金属; 和牺牲层上的上金属层。 牺牲层中的第二金属的电负性大于电介质层中第一金属的电负性。