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    Time-to-digital converter using stochastic phase interpolation
    2.
    发明授权
    Time-to-digital converter using stochastic phase interpolation 有权
    使用随机相位插值的时间 - 数字转换器

    公开(公告)号：US09490831B2

    公开(公告)日：2016-11-08

    申请号：US14817727

    申请日：2015-08-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sung-Jin Kim ,  Jihyun Kim ,  Taeik Kim

    IPC: H03L7/06 ,  H03L7/189 ,  G04F10/00

    CPC classification number: H03L7/189 ,  G04F10/005 ,  H03L7/085 ,  H03L7/18

    Abstract: Provided is a time-to-digital converter. The time-to-digital converter includes several delay circuits, an adder configured to count outputs of the delay circuits, and a least significant bit (LSB) truncation circuit configured to truncate a predetermined number of LSBs from a result output by the adder. The time-to-digital converter is configured to determine a time interval between a start signal and a stop signal within one cycle of a clock having a predetermined period.

    Abstract translation: 提供了一个时间 - 数字转换器。 时间数字转换器包括若干延迟电路，被配置为对延迟电路的输出进行计数的加法器和被配置为从加法器输出的结果中截断预定数量的LSB的最低有效位（LSB）截断电路。 时间数字转换器被配置为在具有预定周期的时钟的一个周期内确定起始信号和停止信号之间的时间间隔。

    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
    3.
    发明申请
    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME 审中-公开
    半导体封装及其制造方法

    公开(公告)号：US20150318270A1

    公开(公告)日：2015-11-05

    申请号：US14796519

    申请日：2015-07-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Taegyu Kang ,  Minchul Kim ,  Sung-Jin Kim ,  Kyeongjun Song

    IPC: H01L25/00 ,  H01L21/56 ,  H01L25/065

    CPC classification number: H01L25/50 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15331 ,  H01L2924/00012

    Abstract: A semiconductor package comprises a lower package comprising a lower substrate, a lower semiconductor chip mounted on a surface of the lower substrate, connection terminals between the lower substrate and the lower semiconductor chip, and a protection film covering the lower semiconductor chip. An upper package is spaced apart from the lower package on an upper surface of the lower substrate, the upper package comprising an upper substrate and an upper semiconductor chip. Connections are present between the lower substrate and the upper substrate to horizontally surround the lower semiconductor chip. A molding film is on the upper surface of the lower substrate to fill spaces between the connection terminals and the connections. An uppermost surface of the protection film is positioned at substantially a same vertical level as an uppermost surface of the molding film and is spaced apart from the upper package.

    Abstract translation: 半导体封装包括下封装，其包括下基板，安装在下基板的表面上的下半导体芯片，下基板和下半导体芯片之间的连接端子以及覆盖下半导体芯片的保护膜。 上封装在下基板的上表面上与下封装隔开，上封装包括上基板和上半导体芯片。 连接存在于下基板和上基板之间以水平地围绕下半导体芯片。 成型膜位于下基板的上表面上，以填充连接端子和连接件之间的空间。 保护膜的最上表面位于与成型膜的最上表面大致相同的垂直高度，并且与上包装件间隔开。

    Current reference circuit and an electronic device including the same
    4.
    发明授权
    Current reference circuit and an electronic device including the same 有权

    公开(公告)号：US09946290B2

    公开(公告)日：2018-04-17

    申请号：US15236931

    申请日：2016-08-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sung-Jin Kim ,  Tae-Ik Kim ,  Ji-Hyun Kim

    IPC: H03L7/08 ,  G05F1/46 ,  G05F1/575 ,  G05F1/08 ,  G05F1/02 ,  G05F3/26

    CPC classification number: G05F3/262

    Abstract: A current reference circuit includes a reference current supply unit configured to generate a reference current having a target current level, a current-frequency converter configured to receive a first temporary reference current corresponding to the reference current from the reference current supply unit and to generate a first comparison clock signal in response to the first temporary reference current, and a first current compensation unit configured to generate a first current compensation signal used for the first temporary reference current to reach the target current level in response to a frequency of a reference clock signal and a frequency of the first comparison clock signal.

    Phase locked loop having dual bandwidth and method of operating the same
    6.
    发明授权
    Phase locked loop having dual bandwidth and method of operating the same 有权
    具有双带宽的锁相环及其操作方法

    公开(公告)号：US09438102B2

    公开(公告)日：2016-09-06

    申请号：US14591453

    申请日：2015-01-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sung-Jin Kim

    IPC: H02M3/07 ,  H03J1/00 ,  H03L7/087 ,  H03L7/089 ,  H03L7/18

    CPC classification number: H02M3/07 ,  H03J1/005 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/18

    Abstract: A phase locked loop having a dual bandwidth is disclosed. The phase locked loop divides a loop filter into a zero filter and a pole filter, disposes the zero filter in front of a phase-frequency detector (PFD), and performs high-pass filtering on a voltage-controlled oscillator (VCO) noise with a maximum bandwidth and performs low-pass filtering on a charge pump noise (CP noise) with a minimum bandwidth to divide the VCO noise and the CP noise.

    Abstract translation: 公开了具有双重带宽的锁相环。 锁相环将环路滤波器分为零滤波器和极点滤波器，将零滤波器置于相位频率检测器（PFD）的前面，并对压控振荡器（VCO）噪声进行高通滤波， 最大带宽，并对具有最小带宽的电荷泵噪声（CP噪声）进行低通滤波，以分频VCO噪声和CP噪声。

    Semiconductor devices including diffusion barriers with high electronegativity metals
    7.
    发明授权
    Semiconductor devices including diffusion barriers with high electronegativity metals 有权
    包括具有高电负性金属的扩散阻挡层的半导体器件

    公开(公告)号：US09455259B2

    公开(公告)日：2016-09-27

    申请号：US14716371

    申请日：2015-05-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Han-Jin Lim ,  Youn-Soo Kim ,  Hyun Park ,  Soon-Gun Lee ,  Eun-Ae Cho ,  Chin-Moo Cho ,  Sung-Jin Kim ,  Seok-Woo Nam

    IPC: H01L27/108 ,  H01L49/02

    CPC classification number: H01L27/10814 ,  H01L28/75 ,  H01L28/91

    Abstract: A semiconductor device includes a capacitor with reduced oxygen defects at an interface between a dielectric layer and an electrode of the capacitor. The semiconductor device includes a lower metal layer; a dielectric layer on the lower metal layer and containing a first metal; a sacrificial layer on the dielectric layer and containing a second metal; and an upper metal layer on the sacrificial layer. An electronegativity of the second metal in the sacrificial layer is greater than an electronegativity of the first metal in the dielectric layer.

    Abstract translation: 半导体器件包括在电介质层和电容器的电极之间的界面处具有减少的氧缺陷的电容器。 半导体器件包括下金属层; 在下金属层上的介电层并含有第一金属; 在介电层上的牺牲层并含有第二金属; 和牺牲层上的上金属层。 牺牲层中的第二金属的电负性大于电介质层中第一金属的电负性。

    Semiconductor Device
    8.
    发明申请
    Semiconductor Device 有权
    半导体器件

    公开(公告)号：US20160079247A1

    公开(公告)日：2016-03-17

    申请号：US14716371

    申请日：2015-05-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Han-Jin Lim ,  Youn-Soo Kim ,  Hyun Park ,  Soon-Gun Lee ,  Eun-Ae Cho ,  Chin-Moo Cho ,  Sung-Jin Kim ,  Seok-Woo Nam

    IPC: H01L27/108 ,  H01L49/02

    CPC classification number: H01L27/10814 ,  H01L28/75 ,  H01L28/91

    Abstract: A semiconductor device includes a capacitor with reduced oxygen defects at an interface between a dielectric layer and an electrode of the capacitor. The semiconductor device includes a lower metal layer; a dielectric layer on the lower metal layer and containing a first metal; a sacrificial layer on the dielectric layer and containing a second metal; and an upper metal layer on the sacrificial layer. An electronegativity of the second metal in the sacrificial layer is greater than an electronegativity of the first metal in the dielectric layer.

    Abstract translation: 半导体器件包括在电介质层和电容器的电极之间的界面处具有减少的氧缺陷的电容器。 半导体器件包括下金属层; 在下金属层上的介电层并含有第一金属; 在介电层上的牺牲层并含有第二金属; 和牺牲层上的上金属层。 牺牲层中的第二金属的电负性大于电介质层中第一金属的电负性。

    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
    9.
    发明申请
    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME 审中-公开
    半导体封装及其制造方法

    公开(公告)号：US20140327155A1

    公开(公告)日：2014-11-06

    申请号：US14134589

    申请日：2013-12-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Taegyu Kang ,  Minchul Kim ,  Sung-Jin Kim ,  Kyeongjun Song

    IPC: H01L23/28 ,  H01L23/00 ,  H01L25/065

    CPC classification number: H01L25/50 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15331 ,  H01L2924/00012

    Abstract: A semiconductor package comprises a lower package comprising a lower substrate, a lower semiconductor chip mounted on a surface of the lower substrate, connection terminals between the lower substrate and the lower semiconductor chip, and a protection film covering the lower semiconductor chip. An upper package is spaced apart from the lower package on an upper surface of the lower substrate, the upper package comprising an upper substrate and an upper semiconductor chip. Connections are present between the lower substrate and the upper substrate to horizontally surround the lower semiconductor chip. A molding film is on the upper surface of the lower substrate to fill spaces between the connection terminals and the connections. An uppermost surface of the protection film is positioned at substantially a same vertical level as an uppermost surface of the molding film and is spaced apart from the upper package.

    Abstract translation: 半导体封装包括下封装，其包括下基板，安装在下基板的表面上的下半导体芯片，下基板和下半导体芯片之间的连接端子以及覆盖下半导体芯片的保护膜。 上封装在下基板的上表面上与下封装隔开，上封装包括上基板和上半导体芯片。 连接存在于下基板和上基板之间以水平地围绕下半导体芯片。 成型膜位于下基板的上表面上，以填充连接端子和连接件之间的空间。 保护膜的最上表面位于与成型膜的最上表面大致相同的垂直高度，并且与上包装件间隔开。

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