公开(公告)号：US20170148797A1

公开(公告)日：2017-05-25

申请号：US15351739

申请日：2016-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Bum KIM ,  Myung-Gil KANG ,  Kang-Hun MOON ,  Cho-Eun LEE ,  Su-Jin JUNG ,  Min-Hee CHOI ,  Yang XU ,  Dong-Suk SHIN ,  Kwan-Heum LEE ,  Hoi-Sung CHUNG

IPC: H01L27/11 ,  H01L29/45 ,  H01L29/161 ,  H01L23/528 ,  H01L27/088 ,  H01L29/08

CPC classification number: H01L27/1104 ,  H01L21/823431 ,  H01L23/485 ,  H01L23/5283 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/66545 ,  H01L29/7848

Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.

公开(公告)号：US20170033797A1

公开(公告)日：2017-02-02

申请号：US15213973

申请日：2016-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Su-Jin JUNG ,  Yongwoo JEON ,  Jangje PARK ,  Sang-Pil LEE

IPC: H03K17/96 ,  H05K1/11 ,  H05K5/00 ,  H05K5/02 ,  G06F1/16 ,  H05K1/18

Abstract: An electronic device is provided. The electronic device includes a housing including a window, configured to form a 1st side of the electronic device, and a 2nd side of the electronic device directed in an opposite direction of the 1st side of the electronic device, a circuit board between the 1st side and the 2nd side of the electronic device, and including an input circuit configured to detect an input based on a change in a capacitance, a spacer between the window and the circuit board, and having at least one space formed on one side facing the circuit board, a contact electrically connected to the input circuit by being mounted to one side of the circuit board, and contained in the at least one space, and a conductive plate coupled to the spacer, and electrically connected to the contact through the at least one space.

Abstract translation: 提供电子设备。 电子设备包括：壳体，其包括构造成形成电子设备的第一侧的窗口，以及电子设备的与电子设备的第一侧相反的方向指向的第二侧，第一侧 和电子设备的第二侧，并且包括被配置为基于电容变化来检测输入的输入电路，窗口和电路板之间的间隔物，并且具有形成在面向电路的一侧上的至少一个空间 电路板，通过安装到电路板的一侧并且容纳在至少一个空间中而与输入电路电连接的触点和耦合到间隔件的导电板，并通过至少一个电连接到触点 空间。

公开(公告)号：US20160293750A1

公开(公告)日：2016-10-06

申请号：US15049859

申请日：2016-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Bum KIM ,  Nam Kyu KIM ,  Hyun-Ho NOH ,  Dong-Chan SUH ,  Byeong-Chan LEE ,  Su-Jin JUNG ,  Jin-Yeong JOE ,  Bon-Young KOO

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/16

CPC classification number: H01L29/785 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848 ,  H01L29/7856

Abstract: A semiconductor device includes an active fin structure extending in a first direction, the active fin structure including protruding portions divided by a recess, a plurality of gate structures extending in a second direction crossing the first direction and covering the protruding portions of the active fin structure, a first epitaxial pattern in a lower portion of the recess between the gate structures, a second epitaxial pattern on a portion of the first epitaxial pattern, the second epitaxial pattern contacting a sidewall of the recess, and a third epitaxial pattern on the first and second epitaxial patterns, the third epitaxial pattern filling the recess. The first epitaxial pattern includes a first impurity region having a first doping concentration, the second epitaxial pattern includes a second impurity region having a second doping concentration lower than the a first doping concentration, and the third epitaxial pattern includes a third impurity region having a third doping concentration higher than the second doping concentration. The semiconductor device may have good electrical characteristics.

Abstract translation: 半导体器件包括沿第一方向延伸的有源鳍结构，所述有源鳍结构包括由凹部分隔的突出部分，沿与第一方向交叉的第二方向延伸并覆盖有源鳍结构的突出部分的多个栅极结构 ，在栅极结构之间的凹部的下部中的第一外延图案，在第一外延图案的一部分上的第二外延图案，第二外延图案接触凹槽的侧壁，以及在第一外延图案的第一和第二外延图案 第二外延图案，填充凹槽的第三外延图案。 第一外延图案包括具有第一掺杂浓度的第一杂质区，第二外延图案包括具有低于第一掺杂浓度的第二掺杂浓度的第二杂质区，并且第三外延图包括具有第三掺杂浓度的第三杂质区 掺杂浓度高于第二掺杂浓度。 半导体器件可具有良好的电特性。

公开(公告)号：US20190221663A1

公开(公告)日：2019-07-18

申请号：US16367813

申请日：2019-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok-Hoon KIM ,  Bon-Young KOO ,  Nam-Kyu KIM ,  Woo-Bin SONG ,  Byeong-Chan LEE ,  Su-Jin JUNG

IPC: H01L29/78 ,  H01L27/12 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08

Abstract: A semiconductor device may include first and second fins formed side by side on a substrate, a first elevated doped region formed on the first fin and having a first doping concentration of impurities, a second elevated doped region formed on the second fin, and a first bridge connecting the first elevated doped region and the second elevated doped region to each other. Methods of manufacturing such a semiconductor device are also disclosed.

公开(公告)号：US20140299934A1

公开(公告)日：2014-10-09

申请号：US14194837

申请日：2014-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok-Hoon KIM ,  Tae-Ouk KWON ,  Su-Jin JUNG ,  Young-Pil KIM ,  Byeong-Chan LEE ,  Bon-Young KOO

IPC: H01L29/78

CPC classification number: H01L29/7848 ,  H01L29/66545 ,  H01L29/785

Abstract: Provided is a semiconductor device. The semiconductor device includes a fin on a substrate; a gate electrode cross the fin on the substrate; a source/drain formed on at least one of both sides of the gate electrode, and including a first film and a second film; and a stress film arranged between an isolation film on the substrate and the source/drain, and formed on a side surface of the fin.

Abstract translation: 提供一种半导体器件。 半导体器件在衬底上包括翅片; 栅电极跨越衬底上的翅片; 源极/漏极，形成在栅电极的两侧中的至少一个上，并且包括第一膜和第二膜; 以及布置在基板上的隔离膜和源极/漏极之间并且形成在鳍的侧表面上的应力膜。

公开(公告)号：US20220415905A1

公开(公告)日：2022-12-29

申请号：US17929513

申请日：2022-09-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Bum KIM ,  Myung-Gil KANG ,  Kang-Hun MOON ,  Cho-Eun LEE ,  Su-Jin JUNG ,  Min-Hee CHOI ,  Yang XU ,  Dong-Suk SHIN ,  Kwan-Heum LEE ,  Hoi-Sung CHUNG

IPC: H01L27/11 ,  H01L23/528 ,  H01L29/66 ,  H01L27/088 ,  H01L29/161 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/78 ,  H01L29/45 ,  H01L29/417 ,  H01L23/485 ,  H01L27/092 ,  H01L29/165

Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.

公开(公告)号：US20170117406A1

公开(公告)日：2017-04-27

申请号：US15398788

申请日：2017-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok-Hoon KIM ,  Bon-Young KOO ,  Nam-Kyu KIM ,  Woo-Bin SONG ,  Byeong-Chan LEE ,  Su-Jin JUNG

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681

Abstract: A semiconductor device may include first and second fins formed side by side on a substrate, a first elevated doped region formed on the first fin and having a first doping concentration of impurities, a second elevated doped region formed on the second fin, and a first bridge connecting the first elevated doped region and the second elevated doped region to each other. Methods of manufacturing such a semiconductor device are also disclosed.

公开(公告)号：US20150162332A1

公开(公告)日：2015-06-11

申请号：US14543140

申请日：2014-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Bum KIM ,  Bon-Young KOO ,  Seok-Hoon KIM ,  Chul KIM ,  Kwan-Heum LEE ,  Byeong-Chan LEE ,  Su-Jin JUNG

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L29/161

CPC classification number: H01L27/0886 ,  H01L29/0653 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/785

Abstract: An integrated circuit device includes an electrically conductive pattern on a substrate. This electrically conductive pattern may be a gate pattern of a field effect transistor. A first electrically insulating spacer is provided on a sidewall of the electrically conductive pattern. The first electrically insulating spacer includes a first lower spacer and a first upper spacer, which extends on the first lower spacer and has a side surface vertically aligned with a corresponding side surface of the first lower spacer. The first upper spacer has a greater dielectric constant relative to a dielectric constant of the first lower spacer. A pair of parallel channel regions may also be provided, which protrude from a surface of the substrate. The electrically conductive pattern may surround top and side surfaces of the pair of parallel channel regions.

Abstract translation: 集成电路器件包括在衬底上的导电图案。 该导电图案可以是场效应晶体管的栅极图案。 第一电绝缘垫片设置在导电图案的侧壁上。 第一电绝缘间隔件包括第一下间隔件和第一上间隔件，其在第一下间隔件上延伸并且具有与第一下间隔件的对应侧表面垂直对准的侧表面。 第一上间隔物相对于第一下间隔物的介电常数具有更大的介电常数。 还可以设置一对平行的通道区域，其从衬底的表面突出。 导电图案可以围绕该对平行通道区域的顶表面和侧表面。