公开(公告)号：US20220115320A1

公开(公告)日：2022-04-14

申请号：US17337212

申请日：2021-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sujeong Kim ,  Inmo Kim

IPC: H01L23/522 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

Abstract: A memory device includes: a memory cell region including gate electrodes spaced apart from each other on a first semiconductor substrate to be stacked, and channel structures; and a peripheral circuit region including upper metal lines disposed above a second semiconductor substrate, disposed below the memory cell region. The first semiconductor substrate includes first regions, having a first value corresponding to a distance between the first semiconductor substrate and the upper metal lines, and second regions having a second value, lower than the first value. A reference voltage for operating the memory device is transmitted to at least one of the first upper metal lines, disposed below the first region. Accordingly, coupling capacitance for a significant signal may be reduced while maintaining a length of a connection portion and the magnitude of resistance of a common source line. Furthermore, an error rate of the memory device may be reduced.

公开(公告)号：US20220139904A1

公开(公告)日：2022-05-05

申请号：US17325821

申请日：2021-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taemin Ok ,  Inmo Kim ,  Sujeong Kim ,  Daeseok Byeon

IPC: H01L27/02 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/06 ,  H01L23/538

Abstract: An integrated circuit device includes a semiconductor substrate having components of a peripheral circuit structure formed in and on a surface of the semiconductor substrate. The peripheral circuit structure comprising a plurality of protective antenna diodes therein. A memory cell array structure is provided on at least a portion of the peripheral circuit structure. A charge accumulating conductive plate is provided, which extends between the peripheral circuit structure and the memory cell array structure. The conductive plate is electrically connected to current carrying terminals of the antenna diodes within the peripheral circuit structure. The conductive plate may have a generally rectangular planar shape with four corners, and the antenna diodes may be arranged into four groups, which extend between respective corners of the conductive plate and the semiconductor substrate.

公开(公告)号：US11862624B2

公开(公告)日：2024-01-02

申请号：US17325821

申请日：2021-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taemin Ok ,  Inmo Kim ,  Sujeong Kim ,  Daeseok Byeon

IPC: H01L27/02 ,  H01L23/538 ,  H01L27/06 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L27/0255 ,  H01L23/5384 ,  H01L23/5386 ,  H01L27/0629 ,  H10B41/27 ,  H10B43/27

Abstract: An integrated circuit device includes a semiconductor substrate having components of a peripheral circuit structure formed in and on a surface of the semiconductor substrate. The peripheral circuit structure comprising a plurality of protective antenna diodes therein. A memory cell array structure is provided on at least a portion of the peripheral circuit structure. A charge accumulating conductive plate is provided, which extends between the peripheral circuit structure and the memory cell array structure. The conductive plate is electrically connected to current carrying terminals of the antenna diodes within the peripheral circuit structure. The conductive plate may have a generally rectangular planar shape with four corners, and the antenna diodes may be arranged into four groups, which extend between respective corners of the conductive plate and the semiconductor substrate.

公开(公告)号：US11830541B2

公开(公告)日：2023-11-28

申请号：US17569679

申请日：2022-01-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daero Kim ,  Kyunghoi Koo ,  Sujeong Kim ,  Juyoung Kim ,  Sanghune Park ,  Jiyeon Park ,  Jihun Oh ,  Kyoungwon Lee

IPC: G11C11/4076 ,  G11C11/4096 ,  G06F13/16 ,  G11C7/10 ,  G11C11/4093 ,  G11C7/14

CPC classification number: G11C11/4096 ,  G11C11/4076 ,  G06F13/1689 ,  G11C7/1066 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/14 ,  G11C11/4093

Abstract: A memory controller includes a first receiver configured to compare a read reference voltage with a piece of data received through a first data line and output a first piece of data; a first duty adjuster configured to adjust a duty of the first piece of data; a second receiver configured to compare the read reference voltage with a piece of data received through a second data line and output a second piece of data; a second duty adjuster configured to adjust a duty of the second piece of data; and a training circuit configured to perform a training operation on pieces of data received through a plurality of data lines, to obtain a target read reference voltage for each piece of data and correct a duty of each piece of data based on a level of the target read reference voltage for each piece of data.

公开(公告)号：US20230171963A1

公开(公告)日：2023-06-01

申请号：US17883272

申请日：2022-08-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungun Lee ,  Inmo Kim ,  Sujeong Kim

IPC: H01L27/11573 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  G11C5/06

CPC classification number: H01L27/11573 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  G11C5/06

Abstract: A semiconductor device includes a memory cell region including a plurality of memory cells disposed on a first semiconductor substrate and including gate electrodes stacked to be spaced apart from each other on the first semiconductor substrate and channel structures passing through the gate electrodes and connected to the first semiconductor substrate, a peripheral circuit region including a first conductivity-type impurity, disposed on a second semiconductor substrate having an upper surface facing each other in a first direction, perpendicular to an upper surface of the first semiconductor substrate, and including peripheral circuits controlling the plurality of memory cells, wherein the peripheral circuits include a plurality of well regions formed in the second semiconductor substrate, an ion implantation region disposed between the plurality of well regions and including the first conductivity-type impurity, and a plurality of antenna diodes, and at least one of the plurality of antenna diodes overlaps the ion implantation region in the first direction. Accordingly, in the semiconductor device according to an exemplary embodiment of the present inventive concept, an antenna diode may be inserted, while minimizing an increase in an interval between the plurality of well regions, and further, peripheral circuits may be integrated and wiring complexity may be reduced.

公开(公告)号：US12119049B2

公开(公告)日：2024-10-15

申请号：US18490042

申请日：2023-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daero Kim ,  Kyunghoi Koo ,  Sujeong Kim ,  Juyoung Kim ,  Sanghune Park ,  Jiyeon Park ,  Jihun Oh ,  Kyoungwon Lee

IPC: G11C11/4076 ,  G11C11/4096 ,  G06F13/16 ,  G11C7/10 ,  G11C7/14 ,  G11C11/4093

CPC classification number: G11C11/4096 ,  G11C11/4076 ,  G06F13/1689 ,  G11C7/1066 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/14 ,  G11C11/4093

Abstract: A memory controller includes a first receiver configured to compare a read reference voltage with a piece of data received through a first data line and output a first piece of data; a first duty adjuster configured to adjust a duty of the first piece of data; a second receiver configured to compare the read reference voltage with a piece of data received through a second data line and output a second piece of data; a second duty adjuster configured to adjust a duty of the second piece of data; and a training circuit configured to perform a training operation on pieces of data received through a plurality of data lines, to obtain a target read reference voltage for each piece of data and correct a duty of each piece of data based on a level of the target read reference voltage for each piece of data.

公开(公告)号：US12189560B2

公开(公告)日：2025-01-07

申请号：US17475705

申请日：2021-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taekyung Yeo ,  Sangyun Hwang ,  Sujeong Kim ,  Jihun Oh ,  Joohee Shin

IPC: G06F13/40 ,  G06F13/42

Abstract: A method of training a physical interface between a first device and a second device includes performing a first training of the physical interface by communicating with the second device by using a first candidate group of lanes from among a plurality of lanes; performing a second training of the physical interface by communicating with the second device by using a second candidate group of lanes from among the plurality of lanes, the second candidate group being different from the first candidate group; determining a lane group based on a result of the first training and a result of the second training; and setting the second device so that the determined lane group is used for the physical interface.

公开(公告)号：US12062606B2

公开(公告)日：2024-08-13

申请号：US17337212

申请日：2021-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sujeong Kim ,  Inmo Kim

IPC: H10B43/40 ,  H01L23/522 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

CPC classification number: H01L23/5226 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

Abstract: A memory device includes: a memory cell region including gate electrodes spaced apart from each other on a first semiconductor substrate to be stacked, and channel structures; and a peripheral circuit region including upper metal lines disposed above a second semiconductor substrate, disposed below the memory cell region. The first semiconductor substrate includes first regions, having a first value corresponding to a distance between the first semiconductor substrate and the upper metal lines, and second regions having a second value, lower than the first value. A reference voltage for operating the memory device is transmitted to at least one of the first upper metal lines, disposed below the first region. Accordingly, coupling capacitance for a significant signal may be reduced while maintaining a length of a connection portion and the magnitude of resistance of a common source line. Furthermore, an error rate of the memory device may be reduced.

公开(公告)号：US20240046982A1

公开(公告)日：2024-02-08

申请号：US18490042

申请日：2023-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daero KIM ,  Kyunghoi Koo ,  Sujeong Kim ,  Juyoung Kim ,  Sanghune Park ,  Jiyeon Park ,  Jihun Oh ,  Kyoungwon Lee

IPC: G11C11/4096 ,  G11C11/4076

CPC classification number: G11C11/4096 ,  G11C11/4076 ,  G06F13/1689

Abstract: A memory controller includes a first receiver configured to compare a read reference voltage with a piece of data received through a first data line and output a first piece of data; a first duty adjuster configured to adjust a duty of the first piece of data; a second receiver configured to compare the read reference voltage with a piece of data received through a second data line and output a second piece of data; a second duty adjuster configured to adjust a duty of the second piece of data; and a training circuit configured to perform a training operation on pieces of data received through a plurality of data lines, to obtain a target read reference voltage for each piece of data and correct a duty of each piece of data based on a level of the target read reference voltage for each piece of data.