-
公开(公告)号:US20230230843A1
公开(公告)日:2023-07-20
申请号:US18095798
申请日:2023-01-11
Applicant: Samsung Electronics Co., Ltd.
Inventor: Taeheon Kim , Kyunghyun Kim , Changsup Mun , Junyoul Yang , Sanghoon Jeong , Yongsik Chung , Seungcheol Chae
IPC: H01L21/311 , H01L29/66
CPC classification number: H01L21/31111 , H01L29/66666 , H10B80/00
Abstract: A wet etching method includes: providing a structure including an etching target film into a process bath containing a first etching solution having a first phosphoric acid concentration; performing a first etching process for etching the etching target film with the first etching solution in the process bath; providing a second etching solution having a second phosphoric acid concentration different from the first phosphoric acid concentration by changing a phosphoric acid concentration in the first etching solution; performing a second etching process for etching the etching target film with the second etching solution in the process bath; providing a third etching solution having a third phosphoric acid concentration different from the first and second phosphoric acid concentrations by changing a phosphoric acid concentration in the second etching solution; and performing a third etching process for etching the etching target film with the third etching solution in the process bath.
-
公开(公告)号:US10580617B2
公开(公告)日:2020-03-03
申请号:US15841230
申请日:2017-12-13
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kijong Park , Jun-Youl Yang , Yongsun Ko , Kyunghyun Kim , Taeheon Kim , Jae Jin Shin
IPC: H01J37/32
Abstract: A plasma etching apparatus includes an etching chamber and at least one processor. The etching chamber is configured to support a target therein. The at least one processor is configured to: determine a process condition for plasma etching the target before execution of a plasma etching process; and control an aspect of the chamber according to the process condition. The process condition includes a unit etching time over which the plasma etching process is to be continuously performed.
-
公开(公告)号:US20170207066A1
公开(公告)日:2017-07-20
申请号:US15133989
申请日:2016-04-20
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kijong PARK , Jun-Youl Yang , Yongsun Ko , Kyunghyun Kim , Taeheon Kim , Jae Jin Shin
IPC: H01J37/32
CPC classification number: H01J37/32009 , H01J37/32449 , H01J37/32899 , H01J37/32926 , H01J37/32935 , H01J37/3299 , H01J2237/334
Abstract: A plasma etching apparatus includes an etching chamber and at least one processor. The etching chamber is configured to support a target therein. The at least one processor is configured to: determine a process condition for plasma etching the target before execution of a plasma etching process; and control an aspect of the chamber according to the process condition. The process condition includes a unit etching time over which the plasma etching process is to be continuously performed.
-
公开(公告)号:US11769755B2
公开(公告)日:2023-09-26
申请号:US17662162
申请日:2022-05-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Eunkyul Oh , Yunrae Cho , Taeheon Kim , Seunghun Han
IPC: H01L21/56 , H01L25/065 , H01L23/00 , H01L23/48 , H01L21/66 , H01L21/768 , H01L21/78 , H01L25/00 , H01L25/18
CPC classification number: H01L25/0657 , H01L21/565 , H01L21/76898 , H01L21/78 , H01L22/12 , H01L22/32 , H01L23/481 , H01L24/14 , H01L25/18 , H01L25/50 , H01L2224/14517 , H01L2225/06513 , H01L2225/06541 , H01L2225/06586 , H01L2225/06596
Abstract: The present disclosure relates to a semiconductor package and a manufacturing method thereof. The method includes stacking semiconductor chips using a thermo-compression bonding (TCB) method, where defects are minimized for increased reliability. The semiconductor package includes an interface chip including a first test pad, a bump pad provided inside the first test pad, and a first through silicon via (TSV) provided between the first test pad and the bump pad; at least one memory chip, which is stacked on the interface chip and includes a second test pad, a dummy pad provided inside the second test pad, and a second TSV provided between the second test pad and the dummy pad; and an adhesive layer provided between the interface chip and the at least one memory chip. wherein no bump is provided on the first test pad and the second test pad.
-
公开(公告)号:US11335668B2
公开(公告)日:2022-05-17
申请号:US16896897
申请日:2020-06-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Eunkyul Oh , Yunrae Cho , Taeheon Kim , Seunghun Han
IPC: H01L23/48 , H01L21/78 , H01L25/065 , H01L23/00 , H01L21/66 , H01L21/56 , H01L21/768 , H01L25/00 , H01L25/18
Abstract: The present disclosure relates to a semiconductor package and a manufacturing method thereof. The method includes stacking semiconductor chips using a thermo-compression bonding (TCB) method, where defects are minimized for increased reliability. The semiconductor package includes an interface chip including a first test pad, a bump pad provided inside the first test pad, and a first through silicon via (TSV) provided between the first test pad and the bump pad; at least one memory chip, which is stacked on the interface chip and includes a second test pad, a dummy pad provided inside the second test pad, and a second TSV provided between the second test pad and the dummy pad; and an adhesive layer provided between the interface chip and the at least one memory chip. wherein no bump is provided on the first test pad and the second test pad.
-
公开(公告)号:US12119329B2
公开(公告)日:2024-10-15
申请号:US18448284
申请日:2023-08-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Eunkyul Oh , Yunrae Cho , Taeheon Kim , Seunghun Han
IPC: H01L23/00 , H01L21/56 , H01L21/66 , H01L21/768 , H01L21/78 , H01L23/48 , H01L25/00 , H01L25/065 , H01L25/18
CPC classification number: H01L25/0657 , H01L21/565 , H01L21/76898 , H01L21/78 , H01L22/12 , H01L22/32 , H01L23/481 , H01L24/14 , H01L25/18 , H01L25/50 , H01L2224/14517 , H01L2225/06513 , H01L2225/06541 , H01L2225/06586 , H01L2225/06596
Abstract: The present disclosure relates to a semiconductor package and a manufacturing method thereof. The method includes stacking semiconductor chips using a thermo-compression bonding (TCB) method, where defects are minimized for increased reliability. The semiconductor package includes an interface chip including a first test pad, a bump pad provided inside the first test pad, and a first through silicon via (TSV) provided between the first test pad and the bump pad; at least one memory chip, which is stacked on the interface chip and includes a second test pad, a dummy pad provided inside the second test pad, and a second TSV provided between the second test pad and the dummy pad; and an adhesive layer provided between the interface chip and the at least one memory chip. wherein no bump is provided on the first test pad and the second test pad.
-
公开(公告)号:US10096453B2
公开(公告)日:2018-10-09
申请号:US15133989
申请日:2016-04-20
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kijong Park , Jun-Youl Yang , Yongsun Ko , Kyunghyun Kim , Taeheon Kim , Jae Jin Shin
IPC: H01J37/32
Abstract: A plasma etching apparatus includes an etching chamber and at least one processor. The etching chamber is configured to support a target therein. The at least one processor is configured to: determine a process condition for plasma etching the target before execution of a plasma etching process; and control an aspect of the chamber according to the process condition. The process condition includes a unit etching time over which the plasma etching process is to be continuously performed.
-
公开(公告)号:US20180102235A1
公开(公告)日:2018-04-12
申请号:US15841230
申请日:2017-12-13
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kijong Park , Jun-Youl Yang , Yongsun Ko , Kyunghyun Kim , Taeheon Kim , Jae Jin Shin
IPC: H01J37/32
CPC classification number: H01J37/32009 , H01J37/32449 , H01J37/32899 , H01J37/32926 , H01J37/32935 , H01J37/3299 , H01J2237/334
Abstract: A plasma etching apparatus includes an etching chamber and at least one processor. The etching chamber is configured to support a target therein. The at least one processor is configured to: determine a process condition for plasma etching the target before execution of a plasma etching process; and control an aspect of the chamber according to the process condition. The process condition includes a unit etching time over which the plasma etching process is to be continuously performed.
-
-
-
-
-
-
-