公开(公告)号：US12021146B2

公开(公告)日：2024-06-25

申请号：US17529406

申请日：2021-11-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hongsik Shin ,  Wonhyuk Lee ,  Dongkwon Kim ,  Jinwook Lee

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/08

CPC classification number: H01L29/7851 ,  H01L27/0886 ,  H01L29/0847

Abstract: Semiconductor devices may include a substrate, an active region that is on the substrate and extends in a first direction, a gate structure that traverses the active region and extends in a second direction that may be different from the first direction, a source/drain region on the active region adjacent a side of the gate structure, an insulating layer on the substrate, the gate structure and the source/drain region, and a contact structure that is in the insulating layer and is connected to the source/drain region. In the source/drain region, a contact region that is in contact with the contact structure includes first and second side regions spaced apart from each other in the second direction and a central region between the first and second side regions, and at least one of the first and second side regions may include a recess.

公开(公告)号：US11211294B2

公开(公告)日：2021-12-28

申请号：US16503728

申请日：2019-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk Lee ,  Jeongyun Lee ,  Yongseok Lee ,  Bosoon Kim ,  Sangduk Park ,  Seungchul Oh ,  Youngmook Oh

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/762 ,  H01L29/08 ,  H01L21/8238

Abstract: A semiconductor device includes a device isolation layer provided on a substrate, the device isolation layer defining first and second sub-active patterns, first and second gate electrodes crossing the first and second sub-active patterns, respectively, and an isolation structure provided on the device isolation layer between the first and second sub-active patterns. The first and second sub-active patterns extend in a first direction and are spaced apart from each other in the first direction. The device isolation layer includes a diffusion break region disposed between the first and second sub-active patterns. The isolation structure covers a top surface of the diffusion break region.

公开(公告)号：US12068242B2

公开(公告)日：2024-08-20

申请号：US17373900

申请日：2021-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongsik Shin ,  Dong Kwon Kim ,  Jinwook Lee ,  Jongchul Park ,  Wonhyuk Lee

IPC: H01L23/522 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L23/5226 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76897 ,  H01L29/6656 ,  H01L29/785 ,  H01L29/78696

Abstract: A semiconductor device including a gate pattern on a substrate and including a gate dielectric layer, a gate electrode, and a gate capping pattern that are sequentially stacked; a gate spacer on a sidewall of the gate pattern; a source/drain pattern in the substrate; a contact pad on the source/drain pattern, a source/drain contact on the contact pad; and a buried dielectric pattern between the gate spacer and the source/drain contact, wherein the gate spacer includes a first segment between the gate electrode and the source/drain pattern; a second segment that extends from the first segment and between the gate electrode and the source/drain contact; and a third segment on the second segment, the buried dielectric pattern is between the third segment and the source/drain contact, and is absent between the first segment and the contact pad and is absent between the second segment and the source/drain contact.

公开(公告)号：US20230335606A1

公开(公告)日：2023-10-19

申请号：US18079057

申请日：2022-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk Lee ,  Sangduk Park ,  Dongsoo Seo ,  Hongsik Shin ,  Jinwook Lee

IPC: H01L29/417 ,  H01L29/40 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L29/41775 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/7851 ,  H01L29/66795 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/775 ,  H01L29/66439

Abstract: A semiconductor device includes a gate structure on a substrate, a gate spacer on a sidewall of the gate structure, a source/drain layer on a portion of the substrate adjacent to the gate structure, and a first contact plug on the source/drain layer and contacting an outer sidewall of the gate spacer. The gate structure includes a first conductive pattern having a lower portion and an upper portion on the lower portion with a width greater than the lower portion and in contact with an inner sidewall of the gate spacer, a second conductive pattern on a lower surface and a sidewall of the lower portion of the first conductive pattern, and a gate insulating pattern on a lower surface and an outer sidewall of the second conductive pattern. An upper surface of the first conductive pattern is substantially coplanar with an upper surface of the first contact plug.

公开(公告)号：US12034060B2

公开(公告)日：2024-07-09

申请号：US17837158

申请日：2022-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongsik Shin ,  Hyunjoon Roh ,  Heungsik Park ,  Sughyun Sung ,  Dohaing Lee ,  Wonhyuk Lee

IPC: H01L29/06 ,  H01L21/306 ,  H01L21/311 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/6656 ,  H01L21/30604 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/42392 ,  H01L29/66553 ,  H01L29/785 ,  H01L29/78696 ,  H01L2029/7858

Abstract: A semiconductor device includes a gate pattern crossing over a substrate, the gate pattern including a gate insulating layer, a gate electrode, and a gate capping pattern sequentially stacked on the substrate, a gate spacer covering a sidewall of the gate pattern, a source/drain pattern on the substrate, the source/drain pattern being adjacent to the sidewall of the gate pattern, a contact pad on the source/drain pattern, a top surface of the contact pad being lower than a top surface of the gate electrode, a source/drain contact plug on the contact pad, and a protection spacer between the gate spacer and the source/drain contact plug, the protection spacer having a ring shape enclosing the source/drain contact plug.

公开(公告)号：US11869811B2

公开(公告)日：2024-01-09

申请号：US17562802

申请日：2021-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk Lee ,  Jeongyun Lee ,  Yongseok Lee ,  Bosoon Kim ,  Sangduk Park ,  Seungchul Oh ,  Youngmook Oh

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/762 ,  H01L29/08 ,  H01L21/8238

CPC classification number: H01L21/823481 ,  H01L21/76224 ,  H01L21/823418 ,  H01L27/088 ,  H01L29/0847 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823814 ,  H01L27/0886

Abstract: A semiconductor device includes a device isolation layer provided on a substrate, the device isolation layer defining first and second sub-active patterns, first and second gate electrodes crossing the first and second sub-active patterns, respectively, and an isolation structure provided on the device isolation layer between the first and second sub-active patterns. The first and second sub-active patterns extend in a first direction and are spaced apart from each other in the first direction. The device isolation layer includes a diffusion break region disposed between the first and second sub-active patterns. The isolation structure covers a top surface of the diffusion break region.

公开(公告)号：US11362196B2

公开(公告)日：2022-06-14

申请号：US16841889

申请日：2020-04-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hongsik Shin ,  Hyunjoon Roh ,  Heungsik Park ,  Sughyun Sung ,  Dohaing Lee ,  Wonhyuk Lee

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L27/088 ,  H01L29/78 ,  H01L21/768 ,  H01L21/311 ,  H01L21/306 ,  H01L21/8234

Abstract: A semiconductor device includes a gate pattern crossing over a substrate, the gate pattern including a gate insulating layer, a gate electrode, and a gate capping pattern sequentially stacked on the substrate, a gate spacer covering a sidewall of the gate pattern, a source/drain pattern on the substrate, the source/drain pattern being adjacent to the sidewall of the gate pattern, a contact pad on the source/drain pattern, a top surface of the contact pad being lower than a top surface of the gate electrode, a source/drain contact plug on the contact pad, and a protection spacer between the gate spacer and the source/drain contact plug, the protection spacer having a ring shape enclosing the source/drain contact plug.

公开(公告)号：US10366927B2

公开(公告)日：2019-07-30

申请号：US15405420

申请日：2017-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonhyuk Lee ,  Jeongyun Lee ,  Yongseok Lee ,  Bosoon Kim ,  Sangduk Park ,  Seungchul Oh ,  Youngmook Oh

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/08 ,  H01L27/088 ,  H01L21/8238

Abstract: A semiconductor device includes a device isolation layer provided on a substrate, the device isolation layer defining first and second sub-active patterns, first and second gate electrodes crossing the first and second sub-active patterns, respectively, and an isolation structure provided on the device isolation layer between the first and second sub-active patterns. The first and second sub-active patterns extend in a first direction and are spaced apart from each other in the first direction. The device isolation layer includes a diffusion break region disposed between the first and second sub-active patterns. The isolation structure covers a top surface of the diffusion break region.