公开(公告)号：US20250029913A1

公开(公告)日：2025-01-23

申请号：US18419084

申请日：2024-01-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaesic LEE ,  Youngbae Kim

IPC: H01L23/498 ,  H01L21/027 ,  H01L23/00

Abstract: A semiconductor package includes: a first semiconductor chip including a first semiconductor layer, and a first connection pad and a first insulation layer that are provided on a surface of the first semiconductor layer extending in a first direction; and a second semiconductor chip including a second semiconductor layer, and a second connection pad and a second insulation layer that are provided on a surface of the second semiconductor layer. The first connection pad directly contacts the second connection pad and is provided on the second connection pad in a second direction that is perpendicular to the first direction. The first insulation layer directly contacts the second insulation layer, the first insulation layer is provided on the second insulation layer in the second direction. A width of the second connection pad in the first direction is smaller than a width of the first connection pad in the first direction.

公开(公告)号：US20240006282A1

公开(公告)日：2024-01-04

申请号：US18345955

申请日：2023-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngbae Kim ,  Seoeun Kyung

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L23/3107 ,  H01L23/49838 ,  H01L23/49822 ,  H01L24/08 ,  H01L2924/1715 ,  H01L2224/08235

Abstract: A semiconductor package includes: a redistribution structure having a first surface and a second surface and including a plurality of redistribution layers, the plurality of redistribution layers including first and second redistribution layers adjacent to the first and second surfaces, respectively,; a semiconductor chip disposed on the first surface; a frame including a wiring structure connected to a first redistribution via of the first redistribution layer; and UBM layers disposed on the second surface and having a plurality of UBM vias. The UBM layers may include at least one UBM layer overlapping the first redistribution via, and the first redistribution via may be disposed so as not to overlap a plurality of UBM vias of the at least one UBM layer and to overlap an internal region closer to a central point of the at least one UBM layer than the plurality of UBM vias.

公开(公告)号：US10985213B2

公开(公告)日：2021-04-20

申请号：US16780014

申请日：2020-02-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Si-Ho Song ,  Youngbae Kim ,  Dueung Kim ,  Changhyun Cho

IPC: H01L27/24 ,  G11C13/00 ,  H01L45/00

Abstract: A nonvolatile memory device includes a memory cell array, a word line drive block that is connected to a first group of memory cells through a first group of word lines and to a second group of memory cells through a second group of word lines, a bit line bias and sense block that is connected to the first and second groups of memory cells through bit lines, a variable current supply block that generates a word line current to be supplied to a selected word line, and a control logic block that receives an address and a command and controls the variable current supply block to adjust an amount of the word line current based on the address. The control logic block further varies the amount of the word line current depending on a distance between the selected word line and the substrate.

公开(公告)号：US10446560B2

公开(公告)日：2019-10-15

申请号：US15986064

申请日：2018-05-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungwoo Kim ,  Bong-Soo Kim ,  Youngbae Kim ,  Kijae Hur ,  Gwanhyeob Koh ,  Hyeongsun Hong ,  Yoosang Hwang

IPC: H01L27/00 ,  H01L27/108 ,  H01L27/24 ,  H01L27/22

Abstract: A semiconductor device including: a first memory section, a first peripheral circuit section, and a second peripheral circuit section on a substrate; a second memory section on the second peripheral circuit section; and a wiring section between the second peripheral circuit section and the second memory section, the first memory section includes a plurality of first memory cells, the first memory cells each including a cell transistor and a capacitor connected to the cell transistor, the second memory section includes a plurality of second memory cells, the second memory cells each including a variable resistance element and a select element in series, and the wiring section includes a plurality of line patterns, at least one of the line patterns and at least one of the capacitors at the same level from the substrate, the second memory cells are higher from the substrate than the at least one of the capacitors.

公开(公告)号：US10395706B2

公开(公告)日：2019-08-27

申请号：US15984914

申请日：2018-05-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungwoo Kim ,  Bong-Soo Kim ,  Youngbae Kim ,  Kijae Hur ,  Gwanhyeob Koh ,  Hyeongsun Hong ,  Yoosang Hwang

IPC: H01L27/00 ,  G11C11/00 ,  H01L23/528 ,  H01L27/108 ,  H01L27/24 ,  H01L49/02 ,  H01L45/00

Abstract: A semiconductor device including: a first memory section, a first peripheral circuit section, and a second peripheral circuit section that are disposed next to each other on a substrate; and a second memory section laterally spaced apart from the first memory section, the second peripheral circuit section and the second memory section disposed next to each other on the substrate, wherein the first memory section includes a plurality of first memory cells, each of the first memory cells including a cell transistor and a capacitor connected to the cell transistor, and the second memory section includes a plurality of second memory cells, each of the second memory cells including a variable resistance element and a select element coupled in series to each other, wherein the second memory cells are higher from the substrate than each of the capacitors.

公开(公告)号：US20200027925A1

公开(公告)日：2020-01-23

申请号：US16354545

申请日：2019-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： SUNG-HO EUN ,  Daehwan Kang ,  Sungwon Kim ,  Youngbae Kim ,  Seokjae Won

IPC: H01L27/24 ,  H01L45/00

Abstract: A variable resistance non-volatile memory device can include a semiconductor substrate and a plurality of first conductive lines each extending in a first direction perpendicular to the semiconductor substrate and spaced apart in a second direction on the semiconductor substrate. A second conductive line can extend in the second direction parallel to the semiconductor substrate on a first side of the plurality of first conductive lines and a third conductive line can extend in the second direction parallel to the semiconductor substrate on a second side of the plurality of first conductive lines opposite the first side of the plurality of first conductive lines. A plurality of first non-volatile memory cells can be on the first side of the plurality of first conductive lines and each can be coupled to the second conductive line and to a respective one of the plurality of first conductive lines, where each of the plurality of first non-volatile memory cells can include a switching element, a variable resistance element, and an electrode arranged in a first sequence. A plurality of second non-volatile memory cells can be on the second side of the plurality of first conductive lines and each can be coupled to the third conductive line and to a respective one of the plurality of first conductive lines, wherein each of the plurality of second non-volatile memory cells includes a switching element, a variable resistance element, and an electrode that are arranged in a second sequence, wherein the first sequence and the second sequence are symmetrical with one another about the plurality of first conductive lines.

公开(公告)号：US10410722B2

公开(公告)日：2019-09-10

申请号：US15987207

申请日：2018-05-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungwoo Kim ,  Bong-Soo Kim ,  Youngbae Kim ,  Kijae Hur ,  Gwanhyeob Koh ,  Hyeongsun Hong ,  Yoosang Hwang

IPC: H01L27/00 ,  G11C14/00 ,  H01L27/24 ,  H01L23/528 ,  H01L45/00 ,  G11C13/00 ,  G11C11/00 ,  G11C5/02 ,  H01L27/108

Abstract: A semiconductor device includes: a first memory section, a first peripheral circuit section, and a second peripheral circuit section that are disposed on a substrate; and a second memory section and a wiring section that are stacked on the second peripheral circuit section, wherein the first memory section includes a plurality of first memory cells, each of the first memory cells including a cell transistor and a capacitor connected to the cell transistor, the second memory section includes a plurality of second memory cells, each of the second memory cells including a variable resistance element and a select element coupled in series to each other, and the wiring section includes a plurality of line patterns, wherein the line patterns and the second memory cells are higher than the capacitor with respect to the substrate.

公开(公告)号：US20190124761A1

公开(公告)日：2019-04-25

申请号：US15966762

申请日：2018-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shle-Ge Lee ,  Youngbae Kim

IPC: H05K1/02 ,  H01L23/00 ,  H01L23/498

Abstract: A printed circuit board can include a base layer, a first surface and a second surface opposite to each other. A first routing layer can be on the first surface and a second routing layer can be on the second surface, the first routing layer can be provided at an upper part of each of the first and second regions and the second routing layer can be provided at a lower part of each of the first and second regions. The upper part of the first region can have a first line-area ratio, the upper part of the second region can have a second line-area ratio, the lower part of the first region can have a third line-area ratio, the lower part of the second region can have a fourth line-area ratio, the second and third line-area ratios can be greater than each of the first and fourth line-area ratios.

公开(公告)号：US09530741B2

公开(公告)日：2016-12-27

申请号：US14712959

申请日：2015-05-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngbae Kim

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L23/562 ,  H01L23/3135 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00014

Abstract: A semiconductor package is provided. The semiconductor includes a lower package and an upper package stacked on the lower package. The lower package includes a package substrate, a semiconductor chip, a mold layer and a residential stress layer. The package substrate has upper and lower surfaces. The semiconductor chip is disposed on the upper surface of the package substrate. The mold layer encapsulates the semiconductor chip. The residual stress layer is disposed on the semiconductor chip. The residual stress layer includes a plastically deformed surface. The residual stress layer has a residual stress to counterbalance warpage of the lower package.

Abstract translation: 提供半导体封装。 半导体包括堆叠在下封装上的下封装和上封装。 下封装包括封装基板，半导体芯片，模层和住宅应力层。 封装衬底具有上表面和下表面。 半导体芯片设置在封装基板的上表面上。 模具层封装半导体芯片。 残余应力层设置在半导体芯片上。 残余应力层包括塑性变形的表面。 残余应力层具有残余应力以平衡下部封装的翘曲。

公开(公告)号：US20240421080A1

公开(公告)日：2024-12-19

申请号：US18438167

申请日：2024-02-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngbae Kim

IPC: H01L23/528 ,  H01L21/66 ,  H01L25/065 ,  H10B80/00

Abstract: A high bandwidth memory structure according to an embodiment may include a buffer die including a plurality of conductive lines, a memory stacking structure on the buffer die, the memory stacking structure includes a plurality of memory dies that are stacked, an interconnection structure between the buffer die and the memory stacking structure, the interconnection structure includes a plurality of connection members and an insulating member surrounding the plurality of connection members, and a plurality of conductive pads disposed on the buffer die and side by side with the plurality of connection members, in which each conductive line of the plurality of conductive lines connect a connection member of the plurality of connection members to a conductive pad of the plurality of conductive pads.