公开(公告)号：US20230402463A1

公开(公告)日：2023-12-14

申请号：US18108125

申请日：2023-02-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoonsung CHOI ,  Youngmok Kim ,  Sangjin Lee

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/8234

CPC classification number: H01L27/1207 ,  H01L21/84 ,  H01L21/823462

Abstract: A semiconductor device includes a bulk substrate including a first region and a second region, a buried oxide layer and a semiconductor layer stacked on the first region, a first gate structure disposed on the semiconductor layer, a first source/drain layer disposed at an upper portion of the semiconductor layer adjacent to the first gate structure, a second gate structure disposed on the second region, and a second source/drain layer disposed at an upper portion of the bulk substrate adjacent to the second gate structure.

公开(公告)号：US09859158B2

公开(公告)日：2018-01-02

申请号：US15239364

申请日：2016-08-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunglyong Kang ,  Youngmok Kim ,  Hodae Oh ,  Kyoung-Eun Uhm

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/28 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L21/76877 ,  H01L21/28123 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/823462 ,  H01L21/823481 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/513 ,  H01L29/517 ,  H01L29/7833

Abstract: A method for manufacturing a semiconductor device includes forming a device isolation layer in a substrate to define an active region, forming a gate insulating layer covering at least a portion of the active region, forming a gate electrode on the gate insulating layer, and forming an interlayer insulating layer on the gate electrode. The gate insulating layer includes a first portion overlapping with the active region and a second portion overlapping with the device isolation layer. The forming of the gate insulating layer includes etching at least a part of the second portion of the gate insulating layer to thin the part of the second portion of the gate insulating layer.

公开(公告)号：US11348504B2

公开(公告)日：2022-05-31

申请号：US17139449

申请日：2020-12-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngmok Kim ,  Kyunglyong Kang ,  Jungu Kang ,  Boyoung Seo ,  Yongsang Jeong

IPC: G09G3/20

Abstract: A display apparatus includes a display panel; and a display driver integrated circuit (DDI) chip coupled to the display panel, the DDI chip being configured to generate a display driving signal for driving the display panel based on image data. The DDI chip may include: a first embedded memory device embedded in the DDI chip and configured to store compensation data for compensating for electrical and optical characteristics of a plurality of pixels included in the display panel; a timing controller configured to control signals for driving the display panel, and to generate a data control signal based on the image data and the compensation data; and a data driver configured to provide a data voltage to the display panel according to the data control signal. The first embedded memory device may not include static random access memory (SRAM).

公开(公告)号：US10937882B2

公开(公告)日：2021-03-02

申请号：US16595187

申请日：2019-10-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeonkwang Lee ,  Sungmin Kang ,  Kyungmin Kim ,  Minhee Uh ,  Jun-Gu Kang ,  Youngmok Kim

IPC: H01L29/06 ,  H01L29/49 ,  H01L27/092 ,  H01L27/12 ,  H01L21/265 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08

Abstract: A semiconductor device includes a substrate, in which a lower semiconductor layer, an insulating gapfill layer, and an upper semiconductor layer are sequentially stacked. A gate structure is disposed on the upper semiconductor layer. A source/drain electrode is disposed on a sidewall of the gate structure. A semiconductor pattern is disposed between the source/drain electrode and the upper semiconductor layer. The gate structure includes a gate electrode and a spacer structure. The spacer structure includes a first spacer pattern, a second spacer pattern, and a third spacer pattern, sequentially disposed on a sidewall of the gate electrode. The semiconductor pattern is extended to a region below a bottom surface of the third spacer pattern and is connected to the second spacer pattern.

公开(公告)号：US11950423B2

公开(公告)日：2024-04-02

申请号：US17306308

申请日：2021-05-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongkyu Lee ,  Youngmok Kim ,  Changmin Jeon ,  Yongsang Jeong

IPC: H01L27/11573 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B43/40 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor device includes: a cell area including a cell substrate, a memory cell array, and a first bonding metal pad on the memory cell array, the memory cell array including a plurality of word lines stacked on the cell substrate and a plurality of bit lines on the plurality of word lines; and a peripheral circuit area having the cell area stacked thereon and including a peripheral circuit substrate, a plurality of circuits on the peripheral circuit substrate, and a second bonding metal pad bonded to the first bonding metal pad, wherein the plurality of circuits include: a plurality of planar channel transistors respectively including a channel along a top surface of the peripheral circuit substrate; and at least one recess channel transistor including a channel along a surface of a recess trench arranged in the peripheral circuit.

公开(公告)号：US20220085048A1

公开(公告)日：2022-03-17

申请号：US17306308

申请日：2021-05-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongkyu Lee ,  Youngmok Kim ,  Changmin Jeon ,  Yongsang Jeong

IPC: H01L27/11573 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582

Abstract: A semiconductor device includes: a cell area including a cell substrate, a memory cell array, and a first bonding metal pad on the memory cell array, the memory cell array including a plurality of word lines stacked on the cell substrate and a plurality of bit lines on the plurality of word lines; and a peripheral circuit area having the cell area stacked thereon and including a peripheral circuit substrate, a plurality of circuits on the peripheral circuit substrate, and a second bonding metal pad bonded to the first bonding metal pad, wherein the plurality of circuits include: a plurality of planar channel transistors respectively including a channel along a top surface of the peripheral circuit substrate; and at least one recess channel transistor including a channel along a surface of a recess trench arranged in the peripheral circuit.

公开(公告)号：US20200303512A1

公开(公告)日：2020-09-24

申请号：US16595187

申请日：2019-10-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YEONKWANG LEE ,  Sungmin Kang ,  Kyungmin Kim ,  Minhee Uh ,  Jun-Gu Kang ,  Youngmok Kim

IPC: H01L29/49 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265

Abstract: A semiconductor device includes a substrate, in which a lower semiconductor layer, an insulating gapfill layer, and an upper semiconductor layer are sequentially stacked. A gate structure is disposed on the upper semiconductor layer. A source/drain electrode is disposed on a sidewall of the gate structure. A semiconductor pattern is disposed between the source/drain electrode and the upper semiconductor layer. The gate structure includes a gate electrode and a spacer structure. The spacer structure includes a first spacer pattern, a second spacer pattern, and a third spacer pattern, sequentially disposed on a sidewall of the gate electrode. The semiconductor pattern is extended to a region below a bottom surface of the third spacer pattern and is connected to the second spacer pattern.