公开(公告)号：US11232038B2

公开(公告)日：2022-01-25

申请号：US16890169

申请日：2020-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ihor Vasyltsov ,  Youngnam Hwang ,  Yongha Park

IPC: G06F12/0875 ,  G11C15/00 ,  G06N20/00

Abstract: A ternary content addressable memory device (TCAM) may include: a cache memory storing a look-up table with respect to a calculation result of a plurality of functions; an approximation unit configured to generate mask bits; and a controller configured to obtain an approximation input value corresponding to an input key based on the mask bits and to retrieve an output value corresponding to the obtained approximation input value from the look-up table.

公开(公告)号：US11012075B2

公开(公告)日：2021-05-18

申请号：US16802927

申请日：2020-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungdal Kwon ,  Seungwook Lee ,  Youngnam Hwang

IPC: H03K19/17 ,  G06F30/32 ,  H03K19/1776 ,  G06F30/327

Abstract: An electronic system and an operation method thereof are disclosed. A method of an electronic system including a field programmable gate array (FPGA) includes: synthesizing, by processing circuitry, code of a high level language into code of a hardware description language; designing, by the processing circuitry, a circuit of an intellectual property (IP) block included in the field programmable gate array according to the code of the hardware description language; and generating, by the processing circuitry, a database containing reference assembly code corresponding to the code of the high level language and information about a circuit configuration of the intellectual property block.

公开(公告)号：US11967952B2

公开(公告)日：2024-04-23

申请号：US17242737

申请日：2021-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungdal Kwon ,  Seungwook Lee ,  Youngnam Hwang

IPC: G06F30/327 ,  H03K19/1776

CPC classification number: H03K19/1776 ,  G06F30/327

Abstract: An electronic system and an operation method thereof are disclosed. A method of an electronic system including a field programmable gate array (FPGA) includes: synthesizing, by processing circuitry, code of a high level language into code of a hardware description language; designing, by the processing circuitry, a circuit of an intellectual property (IP) block included in the field programmable gate array according to the code of the hardware description language; and generating, by the processing circuitry, a database containing reference assembly code corresponding to the code of the high level language and information about a circuit configuration of the intellectual property block.

公开(公告)号：US20230335172A1

公开(公告)日：2023-10-19

申请号：US18177982

申请日：2023-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngnam Hwang

IPC: G11C11/16

CPC classification number: G11C11/1657 ,  G11C11/1655 ,  G11C11/1675 ,  G11C11/1673

Abstract: A memory device and an operating method of the memory device are provided. The memory device includes a plurality of first racetracks each including a series of domains, a bit line driver connected to first sides of ones of the plurality of first racetracks, a first domain index controller configured to shift domains of ones of the plurality of first racetracks, a plurality of first magnetic tunnel junction (MTJ) devices adjacent to the plurality of first racetracks, a plurality of first cell transistors respectively connected to ones of the plurality of first MTJ devices, and a source line driver connected to the plurality of first cell transistors by a plurality of first source lines, wherein the series of domains includes a series of domain sections, and the plurality of first MTJ devices are respectively adjacent to the series of domain sections.

公开(公告)号：US20210142847A1

公开(公告)日：2021-05-13

申请号：US16876563

申请日：2020-05-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-In Kim ,  Youngnam Hwang

IPC: G11C11/4096 ,  G11C11/4097 ,  G11C11/4091 ,  G11C11/408 ,  G11C11/4074 ,  G11C11/56

Abstract: A neuromorphic processor may include at least a first synapse element. The first synapse element may include a first bit cell and a second bit cell, the first bit cell connected to a first bitline, a first inverted bitline, a first wordline, and a first inverted wordline, and the second bit cell connected to the first bitline, the first inverted bitline, a second wordline, and a second inverted wordline. The first synapse element may be configured to receive a first input through the first wordline, the first inverted wordline, the second wordline, and the second inverted wordline, store a first synapse value in the first bit cell and the second bit cell, perform a calculation operation using the first input and the first synapse value, and output a result of the calculation through the first bitline and the first inverted bitline.

公开(公告)号：US08765521B2

公开(公告)日：2014-07-01

申请号：US14143760

申请日：2013-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Jin Kang ,  Youngnam Hwang

IPC: H01L29/02

CPC classification number: H01L45/1683 ,  H01L27/2409 ,  H01L45/06

Abstract: According to example embodiments, a variable resistance memory device include an ohmic pattern on a substrate; a first electrode pattern including a first portion that has a plate shape and contacts a top surface of the ohmic pattern and a second portion that extends from one end of the first portion to a top; a variable resistance pattern electrically connected to the first electrode pattern; and a second electrode pattern electrically connected to the variable resistance pattern, wherein one end of the ohmic pattern and the other end of the first portion are disposed on the same plane.

公开(公告)号：US12229660B2

公开(公告)日：2025-02-18

申请号：US17319679

申请日：2021-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngnam Hwang ,  Jaewon Yang

IPC: G06N3/065 ,  G06F7/544 ,  G06F17/16 ,  G06N3/049

Abstract: A compressed-truncated singular value decomposition (C-TSVD) based crossbar array apparatus is provided. The C-TSVD based crossbar array apparatus may include an original crossbar array in an m×n matrix having row input lines and column output lines and including cells of a resistance memory device, or two partial crossbar arrays obtained by decomposing the original crossbar array based on C-TSVD, an analog to digital converter (ADC) that converts output values of column output lines of sub-arrays obtained through array partitioning, an adder that sums up results of the ADC to correspond to the column output lines, and a controller that controls application of the original crossbar array or the two partial crossbar arrays. Input values are input to the row input lines, a weight is multiplied by the input values and accumulated results are output as output values of the column output lines.

公开(公告)号：US11302392B2

公开(公告)日：2022-04-12

申请号：US16783408

申请日：2020-02-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngnam Hwang

IPC: G11C11/00 ,  G11C13/00 ,  G06N3/063 ,  H03M1/12

Abstract: An analog-to-digital converter is connected to a crossbar array including a plurality of resistive memory cells. Each of the plurality of resistive memory cells includes a resistive element. The analog-to-digital converter includes a voltage generator and processing circuitry. The voltage generator includes at least one resistive memory element including a same resistive material as the resistive element included in the crossbar array, and is configured to generate a first voltage based on a reference voltage and the at least one resistive memory element and to divide the first voltage to generate at least one divided voltage. The processing circuitry is configured to compare a signal voltage generated from the crossbar array with the at least one divided voltage to generate at least one comparison signal and generate at least one digital signal corresponding to the signal voltage based on the at least one comparison signal.

公开(公告)号：US10818347B2

公开(公告)日：2020-10-27

申请号：US16421855

申请日：2019-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ihor Vasyltsov ,  Youngnam Hwang ,  Jinmin Kim ,  Yongha Park ,  Hyunsik Park ,  Jaewon Yang

IPC: G11C11/54 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4096 ,  G06N3/04

Abstract: A semiconductor memory device includes a memory cell array including first memory cells and second memory cell, and a peripheral circuit. When a first command, a first address, and first input data are received, the peripheral circuit reads first data from the first memory cells based on the first address in response to the first command, performs a first operation by using the first data and the first input data, and reads second data from the second memory cells by using a result of the first operation.

公开(公告)号：US12254945B2

公开(公告)日：2025-03-18

申请号：US18204020

申请日：2023-05-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngnam Hwang

IPC: G11C11/54 ,  G11C29/00 ,  G11C29/52

Abstract: A neuromorphic device includes a memory cell array including first resistive memory cells connected to word lines, bit lines and source lines, second resistive memory cells connected to the word lines, at least one redundancy bit line and at least one redundancy source line, third resistive memory cells connected to at least one redundancy word line, the bit lines and the source lines. The memory cell array stores data corresponding to a weight of a neural network in the first resistive memory cells, and is configured to generate a plurality of read currents based on input signals and the data. The neuromorphic device further includes an analog to digital converter (ADC) circuit configured to convert the plurality of read currents into a plurality of digital signals.