公开(公告)号：US10354956B1

公开(公告)日：2019-07-16

申请号：US15863205

申请日：2018-01-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jixin Yu ,  Daxin Mao ,  Hiroyuki Ogawa ,  Johann Alsmeier

IPC: H01L27/28 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L23/528 ,  H01L21/3105 ,  H01L23/532 ,  H01L29/04 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522

Abstract: A contact level silicon oxide layer and a silicon nitride layer is formed over a semiconductor device on a semiconductor substrate. A contact via cavity extending to the semiconductor device is formed. A lower contact via structure portion is formed and recessed between top and bottom surface of the silicon nitride layer. An upper contact via structure portion including a hydrogen diffusion barrier material is formed in a remaining volume of the contact via cavity to provide a contact via structure. A three-dimensional memory array is formed over the silicon nitride layer. Metal interconnect structures are formed to provide electrical connection between the contact via structure and a node of the three-dimensional memory array. The hydrogen diffusion barrier material and the silicon nitride layer block downward diffusion of hydrogen.

公开(公告)号：US10217746B1

公开(公告)日：2019-02-26

申请号：US15867881

申请日：2018-01-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tae-Kyung Kim ,  Raghuveer S. Makala ,  Yanli Zhang ,  Hiroyuki Kinoshita ,  Daxin Mao ,  Jixin Yu ,  Yiyang Gong ,  Kazuto Watanabe ,  Michiaki Sano ,  Haruki Urata ,  Akira Takahashi

IPC: H01L27/105 ,  H01L21/768 ,  H01L27/24 ,  H01L23/535 ,  H01L45/00

Abstract: A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a top surface of a substrate, such that each of the first insulating layers and the first electrically conductive layers includes a respective horizontally-extending portion and a respective non-horizontally-extending portion, memory stack structures extending through a memory array region of the first alternating stack that includes the horizontally-extending portions of the first electrically conductive layers, such that each of the memory stack structures comprises a memory film and a vertical semiconductor channel, a mesa structure located over the substrate, such that each respective non-horizontally-extending portion of the first insulating layers and the first electrically conductive layers is located over a sidewall of the mesa structure, and contact structures that contact a respective one of the non-horizontally-extending portions of the first electrically conductive layers.

公开(公告)号：US10020363B2

公开(公告)日：2018-07-10

申请号：US15458269

申请日：2017-03-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroyuki Ogawa ,  Yasuo Kasagi ,  Satoshi Shimizu ,  Kazuyo Matsumoto ,  Yohei Masamori ,  Jixin Yu ,  Tong Zhang ,  James Kai

IPC: H01L29/10 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

CPC classification number: H01L29/1037 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: Sacrificial semiconductor material portions are connected by a sacrificial semiconductor line extending along a different horizontal direction and protruding into an underlying source conductive layer. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through the sacrificial semiconductor material portions. A backside trench can be formed through the vertically alternating stack employing the sacrificial semiconductor line as an etch stop structure. Source strap material portions providing lateral electrical contact to semiconductor channels of the memory stack structures can be formed by replacement of sacrificial semiconductor material portions and the sacrificial semiconductor line with source strap material portions. Structural-reinforcement portions may be employed to provide structural stability during the replacement process.

公开(公告)号：US10854629B2

公开(公告)日：2020-12-01

申请号：US16368007

申请日：2019-03-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chun Ge ,  Jixin Yu ,  Fabo Yu ,  Xin Yuan Li ,  Yanli Zhang

IPC: H01L27/11578 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11558 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11519

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. A staircase region having stepped surfaces is formed by patterning the alternating stack. Memory opening fill structures are formed in a memory array region, and support pillar structures are formed in the staircase region. Each of the memory stack structures includes a memory film and a vertical semiconductor channel. The support pillar structures include first support pillar structures and having a first maximum lateral dimension and second support pillar structures having a second maximum lateral dimension that is less than the first maximum lateral dimension and interlaced with the first support pillar structures. The sacrificial material layers are replaced with electrically conductive layers. The second support pillar structures are positioned interstitially among the first support pillar structures and contact via structures that are formed on the electrically conductive layers to provide additional structural support.

公开(公告)号：US20200295029A1

公开(公告)日：2020-09-17

申请号：US16889030

申请日：2020-06-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jixin Yu ,  Tae-Kyung Kim ,  Johann Alsmeier ,  Yan Li ,  Jian Chen

IPC: H01L27/11578 ,  G11C5/02 ,  G11C5/06

Abstract: Three-dimensional memory devices in the form of a memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack, in which each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. Bit lines are electrically connected to an end portion of a respective one of the vertical semiconductor channels. Bump connection via structures contact a top surface of a respective one of the bit lines, in which each of the bump connection via structures has a greater lateral dimension along a lengthwise direction of the bit lines than along a widthwise direction of the bit lines. Metallic bump structures of another semiconductor die contact respective ones of the bump connection via structures to make respective electrical connections between the two dies.

公开(公告)号：US20180261671A1

公开(公告)日：2018-09-13

申请号：US15976442

申请日：2018-05-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kazuyo Matsumoto ,  Yasuo Kasagi ,  Satoshi Shimizu ,  Hiroyuki Ogawa ,  Yohei Masamori ,  Jixin Yu ,  Tong Zhang ,  James Kai

IPC: H01L29/10 ,  H01L27/11529 ,  H01L27/11573 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157

CPC classification number: H01L29/1037 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A etch stop semiconductor rail is formed within a source semiconductor layer. A laterally alternating stack of dielectric rails and sacrificial semiconductor rails is formed over the source semiconductor layer and the etch stop semiconductor rail. After formation of a vertically alternating stack of insulating layers and spacer material layers, memory stack structures are formed through the vertically alternating stack and through interfaces between the sacrificial semiconductor rails and the dielectric rails. A backside trench is formed through the vertically alternating stack employing the etch stop semiconductor rail as an etch stop structure. Source strap rails providing lateral electrical contact to semiconductor channels of the memory stack structures are formed by replacement of sacrificial semiconductor rails with source strap rails.

公开(公告)号：US10008570B2

公开(公告)日：2018-06-26

申请号：US15458272

申请日：2017-03-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jixin Yu ,  Kento Kitamura ,  Tong Zhang ,  Chun Ge ,  Yanli Zhang ,  Satoshi Shimizu ,  Yasuo Kasagi ,  Hiroyuki Ogawa ,  Daxin Mao ,  Kensuke Yamaguchi ,  Johann Alsmeier ,  James Kai

IPC: H01L29/10 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

CPC classification number: H01L29/1037 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: The contact area between a source strap structure of a buried source layer and semiconductor channels within memory structures can be increased by laterally expanding a source-level volume in which the memory stack structures are formed. In one embodiment, sacrificial semiconductor pedestals can be formed in source-level memory openings prior to formation of a vertically alternating stack of insulating layers and sacrificial material layers. Memory openings can include bulging portions formed by removal of the sacrificial semiconductor pedestals. Memory stack structures can be formed with a greater sidewall surface area in the bulging portions to provide a greater contact area with the source strap structure. Alternatively, bottom portions of memory openings can be expanded selective to upper portions during, or after, formation of the memory openings to provide bulging portions and to increase the contact area with the source strap structure.

公开(公告)号：US20170179151A1

公开(公告)日：2017-06-22

申请号：US15268946

申请日：2016-09-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James Kai ,  Jin Liu ,  Johann Alsmeier ,  Jixin Yu ,  Yoko Furihata ,  Hiroyuki Ogawa

IPC: H01L27/115 ,  H01L21/768 ,  H01L27/02 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L27/11582 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/0288 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

Abstract: A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via structures which electrically couple the word lines in a first memory block to the word line driver devices. The through-memory-level via structures extend through a through-memory-level via region located between a staircase region of the first memory block and a staircase region of another memory block.

公开(公告)号：US11380707B2

公开(公告)日：2022-07-05

申请号：US17116093

申请日：2020-12-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Koichi Matsuno ,  Jixin Yu ,  Johann Alsmeier

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/1157 ,  H01L27/11565

Abstract: A three-dimensional memory device includes layer stacks located over a substrate and laterally spaced apart from each other by backside trenches. Each of the layer stacks includes a respective alternating stack of insulating layers and electrically conductive layers. Memory openings vertically extend through a respective one of the alternating stacks and are filled with a respective memory opening fill structure. Each of the memory opening fill structures includes a respective vertical semiconductor channel and a respective vertical stack of memory elements. Each backside trench fill structure includes a respective row of backside trench bridge structures that are more distal from the substrate than a most distal one of the electrically conductive layers is from the substrate. The backside trench bridge structures can provide structural support during a replacement process that forms the electrically conductive layers.

公开(公告)号：US20200312865A1

公开(公告)日：2020-10-01

申请号：US16368007

申请日：2019-03-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chun Ge ,  Jixin Yu ,  Fabo Yu ,  Xin Yuan Li ,  Yanli Zhang

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11558

Abstract: An alternating stack of insulating layers and spacer material layers is formed over a substrate. A staircase region having stepped surfaces is formed by patterning the alternating stack. Memory opening fill structures are formed in a memory array region, and support pillar structures are formed in the staircase region. Each of the memory stack structures includes a memory film and a vertical semiconductor channel. The support pillar structures include first support pillar structures and having a first maximum lateral dimension and second support pillar structures having a second maximum lateral dimension that is less than the first maximum lateral dimension and interlaced with the first support pillar structures. The sacrificial material layers are replaced with electrically conductive layers. The second support pillar structures are positioned interstitially among the first support pillar structures and contact via structures that are formed on the electrically conductive layers to provide additional structural support.