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    Non-volatile memory with one sided phased ramp down after program-verify
    2.
    发明授权
    Non-volatile memory with one sided phased ramp down after program-verify 有权

    公开(公告)号：US11972819B2

    公开(公告)日：2024-04-30

    申请号：US17872148

    申请日：2022-07-25

    Applicant: SanDisk Technologies LLC

    Inventor： Jiacen Guo ,  Peng Zhang ,  Xiang Yang ,  Yanli Zhang

    IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24

    CPC classification number: G11C16/3459 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/102 ,  G11C16/24

    Abstract: In a non-volatile memory system that performs programming of selected memory cells (in coordination with pre-charging and boosting of channels for unselected memory cells) and program-verify to determine whether the programming was successful, the system transitions from program-verify to the next dose of programming by concurrently lowering a voltage applied to a selected word line and voltages applied to word lines on a first side of the selected word line at the conclusion of program-verify. Subsequent to lowering the voltage applied to the selected word line, the system successively lowers voltages applied to groups of one or more word lines on a second side of the selected word line at the conclusion of program-verify beginning with a group of one or more word lines immediately adjacent the selected word line and progressing to other groups of one or more word lines disposed increasingly remote from the selected word line.

    HOLE PRE-CHARGE SCHEME USING GATE INDUCED DRAIN LEAKAGE GENERATION
    3.
    发明申请
    HOLE PRE-CHARGE SCHEME USING GATE INDUCED DRAIN LEAKAGE GENERATION 有权

    公开(公告)号：US20210408024A1

    公开(公告)日：2021-12-30

    申请号：US16916186

    申请日：2020-06-30

    Applicant: SanDisk Technologies LLC

    Inventor： Sarath Puthenthermadam ,  Yanli Zhang ,  Huai-yuan Tseng ,  Peng Zhang

    IPC: H01L27/11556 ,  G11C5/02 ,  G11C5/06 ,  H01L29/06 ,  H01L27/11582

    Abstract: A memory device disclosed herein. The memory device comprises: a memory string including a first select transistor, a memory cell transistor, and a second select transistor connected in series; a bit line connected to one end of the first select transistor; a source line connected to one end of the second select transistor; a first select line connected to a gate of the first select transistor; a word line connected to a gate of the memory cell transistor; a second select line connected to a gate of the second select transistor; and a control circuit configured to perform, before a program operation, a pre-charge operation comprising: applying a voltage to the second select line connected to the gate of the second select transistor to cause gate-induced drain leakage from the second select transistor.

    CHANNEL PRE-CHARGE PROCESS IN A MEMORY DEVICE
    6.
    发明公开
    CHANNEL PRE-CHARGE PROCESS IN A MEMORY DEVICE 审中-公开

    公开(公告)号：US20240203511A1

    公开(公告)日：2024-06-20

    申请号：US18221649

    申请日：2023-07-13

    Applicant: SanDisk Technologies LLC

    Inventor： Jiacen Guo ,  Peng Zhang ,  Xiang Yang ,  Yanli Zhang

    IPC: G11C16/34 ,  G11C16/08 ,  G11C16/10

    CPC classification number: G11C16/3459 ,  G11C16/08 ,  G11C16/102

    Abstract: The memory device includes a memory block with memory cells arranged in word lines that are divided into sub-blocks. Control circuitry is configured to program each of the word lines of a selected sub-blocks in a plurality of program loops. During at least one program loop, the control circuitry applies a programming pulse to a selected word line. The control circuitry is also configured to simultaneously apply a verify voltage to the selected word line and a pass voltage to unselected word lines. In a first phase of a multi-phase pre-charge process, the control circuitry reduces the voltages applied to the selected word line and at least one unprogrammed word line to a low voltage. In a second phase that follows the first phase, the control circuitry reduces the voltages applied to all word lines that remained at the pass voltage to the low voltage.

    GATE-INDUCED DRAIN LEAKAGE PRE-CHARGE IN SUB-BLOCK MODE FOR THREE OR MORE TIER NON-VOLATILE MEMORY STRUCTURE
    7.
    发明公开
    GATE-INDUCED DRAIN LEAKAGE PRE-CHARGE IN SUB-BLOCK MODE FOR THREE OR MORE TIER NON-VOLATILE MEMORY STRUCTURE 审中-公开

    公开(公告)号：US20240112743A1

    公开(公告)日：2024-04-04

    申请号：US17956409

    申请日：2022-09-29

    Applicant: SanDisk Technologies LLC

    Inventor： Peng Zhang ,  Yanli Zhang

    IPC: G11C16/34 ,  G11C16/08 ,  G11C16/24 ,  G11C16/28

    CPC classification number: G11C16/3459 ,  G11C16/08 ,  G11C16/24 ,  G11C16/28

    Abstract: An apparatus includes memory cells connected to word lines and disposed in strings each defining a channel and coupled to bit lines and a source line. The memory cells are configured to retain a threshold voltage corresponding to data states. A control means is configured to apply programming pulses followed by verification pulses of program verify voltages associated with the data states to the word lines during a program operation. The control means ramps a selected word line voltage applied to the word lines from one of the program verify voltages to approximately zero while ramping voltages applied to the bit lines and the source line to a high supply voltage during a pre-charge operation. The control means ramps an assist voltage applied to a pre-charge assist portion of the memory apparatus to generate gate-induced drain leakage current in the strings and pre-charge the channel during the pre-charge operation.

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