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公开(公告)号:US20230100058A1
公开(公告)日:2023-03-30
申请号:US17955955
申请日:2022-09-29
申请人: Semiconductor Manufacturing International (Beijing) Corporation , Semiconductor Manufacturing International (Shanghai) Corporation
发明人: Hailong YU , Bo SU , Hansu OH
IPC分类号: H01L29/66 , H01L29/06 , H01L29/423 , H01L29/417 , H01L29/775 , H01L21/02 , H01L21/311 , H01L21/285
摘要: Semiconductor structure and forming method thereof are provided. The forming method includes: providing a substrate; forming a plurality of initial composite layers on a portion of the substrate; forming a plurality of source and drain layers on surfaces of the plurality of channel layers exposed by a first opening and grooves by using a selective epitaxial growth process, the plurality of source and drain layers being parallel to a first direction and distributed along a second direction, the second direction being parallel to a normal direction of the substrate, and gaps being between adjacent source and drain layers; forming contact layers on surfaces of the plurality of source and drain layers and in the gaps; and forming a conductive structure on a surface of a contact layer on a source and drain layer of the plurality of source and drain layers.
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公开(公告)号:US20230238449A1
公开(公告)日:2023-07-27
申请号:US18124768
申请日:2023-03-22
申请人: Semiconductor Manufacturing International (Shanghai) Corporation , Semiconductor Manufacturing International (Beijing) Corporation
IPC分类号: H01L29/66 , H01L21/768 , H01L21/311
CPC分类号: H01L29/66545 , H01L21/31116 , H01L21/76834 , H01L21/76877 , H01L21/76897 , H01L29/6656
摘要: A semiconductor structure and a forming method therefor are provided. The forming method includes: providing a base, a gate structure, a source/drain doped area, and a bottom dielectric layer; forming a source/drain interconnect layer running through the bottom dielectric layer on a top of the source/drain doped area; forming a top dielectric layer on the bottom dielectric layer; forming a gate contact running through the top dielectric layer on a top of the gate structure and a source/drain contact running through the top dielectric layer on a top of the source/drain interconnect layer; forming a sacrificial side wall layer on side walls of the gate contact and the source/drain contact; forming a gate plug filling the gate contact and a source/drain plug filling the source/drain contact; removing the sacrificial side wall layer to form a first gap; and forming a sealing layer sealing the first gap.
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公开(公告)号:US20230223452A1
公开(公告)日:2023-07-13
申请号:US18124058
申请日:2023-03-21
申请人: Semiconductor Manufacturing International (Shanghai) Corporation , Semiconductor Manufacturing International (Beijing) Corporation
发明人: Bo Su , Hansu OH , Chunsheng ZHENG , Erhu ZHENG , Haiyang ZHANG
IPC分类号: H01L29/417 , H01L29/66 , H01L27/092 , H01L21/8238 , H01L29/78
CPC分类号: H01L29/41791 , H01L29/66545 , H01L27/0924 , H01L21/823864 , H01L21/823814 , H01L29/66795 , H01L29/7851
摘要: A semiconductor structure and a forming method thereof are provided. The method includes: providing a substrate, a dummy spacer being formed on a side wall of the gate structure, a contact etch stop layer being formed on a side wall of the dummy spacer, and a source/drain doped area being formed in the substrate on two sides of the gate structure; forming a sacrificial dielectric layer above tops of the source/drain doped area and the gate structure; forming a source/drain plug running through the sacrificial dielectric layer; etching the sacrificial dielectric layer until a top of the dummy spacer is exposed; removing, after the top of the dummy spacer is exposed, the dummy spacer to form a gap between the contact etch stop layer and the side wall of the gate structure; and forming a top dielectric layer filling between the source/drain plugs.
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公开(公告)号:US20220199808A1
公开(公告)日:2022-06-23
申请号:US17226462
申请日:2021-04-09
申请人: Semiconductor Manufacturing International (Shanghai) Corporation , Semiconductor Manufacturing International (Beijing) Corporation
发明人: Hansu OH , Pengchong LI , Xuejie SHI , Yiyu CHEN , Bo SU
IPC分类号: H01L29/66 , H01L29/78 , H01L21/8234
摘要: A semiconductor structure and a method for forming the same are provided. In one form, a forming method includes: providing a base, a gate structure, a source-drain doping region, and an interlayer dielectric layer; removing the gate structure located in an isolation region to form an isolation opening and expose the top and side walls of a fin located in the isolation region; performing first ion-doping on the fin under the isolation opening to form an isolation doped region, a doping type of the isolation doped region being different from a doping type of the source-drain doping region; and filling the isolation opening with an isolation structure after the doping, the isolation structure straddling the fin of the isolation region. In embodiments and implementations of the present disclosure, the isolation doped region is formed, a doping concentration of inversion ions in the fin of the isolation region can thus be increased, and a barrier of a P-N junction formed by the source-drain doping region and the fin of the isolation region can be increased accordingly, to prevent the device from generating a conduction current in the fin of the isolation region during operation, thereby implementing isolation between the fin of the isolation region and the fin of other regions. Moreover, there is no need to perform a fin cut process. Hence the fin is made into a continuous structure, which helps prevent stress relief in the fin.
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公开(公告)号:US20220199460A1
公开(公告)日:2022-06-23
申请号:US17520967
申请日:2021-11-08
申请人: Semiconductor Manufacturing International (Shanghai) Corporation , Semiconductor Manufacturing International (Beijing) Corporation
发明人: Pengchong LI , Xuejie SHI , Hansu OH , Bo SU
IPC分类号: H01L21/762 , H01L21/265 , H01L21/8234 , H01L29/66
摘要: A method for forming a semiconductor structure is provided. In one form, a method includes: providing a base, a dummy gate structure, a source-drain doped region, and an interlayer dielectric layer; removing the dummy gate structure located at an isolation region to form an isolation opening; performing first ion doping on a fin below the isolation opening, to form an isolation doped region, where a doping type of the isolation doped region is different from a doping type of the source-drain doped region; filling an isolation structure in the isolation opening; removing the remaining dummy gate structure, to form a gate opening; and forming a gate structure in the gate opening. In embodiments and implementations of the present disclosure, the isolation doped region with a doping type different from that of the source-drain doped region is formed, so that a doping concentration of opposite-type ions in the fin of the isolation region can be improved, thereby accordingly improving a potential energy barrier of a P-N junction formed by the source-drain doped region and the fin of the isolation region, to prevent a conduction current from being generated in the fin of the isolation region when a device is working, and implementing isolation between the fin in the isolation region and the fin in other regions. Moreover, there is no need to perform a fin cut process, so that the fin is a continuous structure, to prevent stress release in the fin.
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公开(公告)号:US20240332400A1
公开(公告)日:2024-10-03
申请号:US18615032
申请日:2024-03-25
IPC分类号: H01L29/66 , H01L29/06 , H01L29/423 , H01L29/775 , H01L29/786
CPC分类号: H01L29/66553 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696
摘要: A semiconductor structure includes: a channel protrusion structure, suspended on a base, including channel layers arranged at intervals along a longitudinal direction; a gate structure, spanning the channel protrusion structure and covering part of a top and part of a side wall of the channel protrusion structure, surrounding and covering the channel layers, the gate structure located between adjacent channel layers in the longitudinal direction and between adjacent channel layers and the base serving as an inner gate structure, and the inner gate structure and the adjacent channel layers, and/or, the inner gate structure, the adjacent channel layers and the base forming an inner trench; an inner spacer, located in the inner trench; and a source/drain doped layer, located on the base and connected to two ends of the channel layer, the source/drain doped layer and the inner spacer having a gap therebetween used as an air spacer.
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公开(公告)号:US20240063298A1
公开(公告)日:2024-02-22
申请号:US18234210
申请日:2023-08-15
发明人: Bo SU , Hailong YU , Jing ZHANG , Hansu OH
IPC分类号: H01L29/775 , H01L29/06 , H01L29/423 , H01L29/66
CPC分类号: H01L29/775 , H01L29/0673 , H01L29/42392 , H01L29/66545 , H01L29/66553 , H01L29/66439
摘要: A semiconductor structure includes a plurality of composite layers formed on a portion of a substrate. An interlayer dielectric layer is formed on the substrate and the plurality of composite layers. A first gate trench is formed on the interlayer dielectric layer, and a gate sidewall is formed on a side surface of the first gate trench. The composite layer includes stacked channel layers and a second gate trench between neighboring channel layers. The first gate trench and the gate sidewall cross over a portion of a sidewall and a portion of a top surface of the composite layer, and the first gate trench communicates with the second gate trench. A gate is formed in the first and second gate trenches. The doping region is formed in a channel layer. The source-drain layer is formed in the composite layer on two sides of the gate structure.
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公开(公告)号:US20230369328A1
公开(公告)日:2023-11-16
申请号:US18127736
申请日:2023-03-29
发明人: Bo SU , Abraham YOO , Hansu OH , Byung Sup SHIM
IPC分类号: H01L27/092 , H01L29/06 , H01L29/423 , H01L29/775 , H01L21/8238 , H01L29/66
CPC分类号: H01L27/092 , H01L29/0673 , H01L29/42392 , H01L29/775 , H01L21/823807 , H01L21/823814 , H01L29/66439 , H01L29/66545
摘要: A semiconductor structure and a method for forming the same are provided. The method includes: removing a partial thickness of a first channel layer in an N-type region along a direction parallel to the substrate, to form a first trench, where the first trench is defined by the remaining first channel layer and an adjacent sacrificial layer or by the remaining first channel layer and the adjacent sacrificial layer and a limiting layer; filling the first trench with a sidewall channel film; removing the remaining first channel layer in the N-type region, so that a second trench is defined between the sidewall channel film and the adjacent sacrificial layer or between the sidewall channel film and the adjacent sacrificial layer and the limiting layer; and filling the second trench with a center channel film, where the center channel film and the sidewall channel film are in contact with each other to form a second channel layer, and the second channel layer is configured to improve carrier mobility in a channel of an NMOS transistor. Embodiments of the present disclosure improve performance of a semiconductor structure.
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