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    Conformal liner for gap-filling
    2.
    发明申请
    Conformal liner for gap-filling 审中-公开
    用于间隙填充的保形衬套

    公开(公告)号：US20080096364A1

    公开(公告)日：2008-04-24

    申请号：US11582442

    申请日：2006-10-18

    申请人： Erik Wilson ,  Minh-Van Ngo ,  Hieu Pham ,  Robert Huertas ,  Lu You ,  Hirokazu Tokuno ,  Alexander Nickel ,  Minh Tran

    发明人： Erik Wilson ,  Minh-Van Ngo ,  Hieu Pham ,  Robert Huertas ,  Lu You ,  Hirokazu Tokuno ,  Alexander Nickel ,  Minh Tran

    IPC分类号： H01L21/76

    CPC分类号： H01L21/823468 ,  H01L21/76829 ,  H01L21/76837 ,  H01L21/823437

    摘要： Gap filling between features which are closely spaced is significantly improved by initially depositing a thin conformal layer followed by depositing a layer of gap filling dielectric material. Embodiments include depositing a thin conformal layer of silicon nitride or silicon oxide, as by atomic layer deposition or pulsed layer deposition, into the gap between adjacent gate electrode structures such that it flows into undercut regions of dielectric spacers on side surfaces of the gate electrode structures, and then depositing a layer of BPSG or P-HDP oxide on the thin conformal layer into the gap. Embodiments further include depositing the layers at a temperature less than 430° C., as by depositing a P-HDP oxide after depositing the conformal liner when the gate electrode structures include a layer of nickel silicide.

    摘要翻译： 通过初始沉积薄的共形层，然后沉积一层间隙填充电介质材料，密切间隔的特征之间的间隙填充显着改善。 实施例包括通过原子层沉积或脉冲层沉积将氮化硅或氧化硅的薄保形层沉积到相邻栅电极结构之间的间隙中，使得其流到栅电极结构的侧表面上的电介质间隔物的底切区域 ，然后在薄的共形层上沉积一层BPSG或P-HDP氧化物到间隙中。 实施例还包括在低于430℃的温度下沉积层，如通过在栅极电极结构包括硅化镍层沉积保形衬垫之后沉积P-HDP氧化物。

    Gap-filling with uniform properties
    4.
    发明授权
    Gap-filling with uniform properties 有权
    间隙填充均匀性

    公开(公告)号：US08415256B1

    公开(公告)日：2013-04-09

    申请号：US12982364

    申请日：2010-12-30

    申请人： Alexander Nickel ,  Lu You ,  Hirokazu Tokuno ,  Minh Tran ,  Minh Van Ngo ,  Hieu Pham ,  Erik Wilson ,  Robert Huertas

    发明人： Alexander Nickel ,  Lu You ,  Hirokazu Tokuno ,  Minh Tran ,  Minh Van Ngo ,  Hieu Pham ,  Erik Wilson ,  Robert Huertas

    IPC分类号： H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/022 ,  H01L21/02348 ,  H01L21/76224 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76837

    摘要： During semiconductor fabrication homogeneous gap-filling is achieved by depositing a thin dielectric layer into the gap, post deposition curing, and then repeating deposition and post deposition curing until gap-filling is completed. Embodiments include depositing a layer of low deposition temperature gap-fill dielectric into a high aspect ratio opening, such as a shallow trench or a gap between closely spaced apart gate electrode structures, as at a thickness of about 10 Å to about 500 Å, curing after deposition, as by UV radiation or by heating at a temperature of about 400° C. to about 1000° C., depositing another layer of low deposition temperature gap-filled dielectric, and curing after deposition. Embodiments include separately depositing and separately curing multiple layers.

    摘要翻译： 在半导体制造期间，通过将薄介电层沉积到间隙中，后沉积固化，然后重复沉积和后沉积固化直到间隙填充完成来实现均匀间隙填充。 实施例包括将低沉积温度间隙填充电介质的层沉积到高纵横比开口中，例如浅沟槽或紧密间隔开的栅电极结构之间的间隙，其厚度约为至约500，固化 在沉积之后，如通过UV辐射或在约400℃至约1000℃的温度下加热，沉积另一层低沉积温度充满间隙的电介质，并在沉积后固化。 实施例包括分别沉积和分别固化多层。

    Gap-filling with uniform properties
    5.
    发明授权
    Gap-filling with uniform properties 有权
    间隙填充均匀性

    公开(公告)号：US07884030B1

    公开(公告)日：2011-02-08

    申请号：US11408086

    申请日：2006-04-21

    申请人： Alexander Nickel ,  Lu You ,  Hirokazu Tokuno ,  Minh Tran ,  Minh Van Ngo ,  Hieu Pham ,  Erik Wilson ,  Robert Huertas

    发明人： Alexander Nickel ,  Lu You ,  Hirokazu Tokuno ,  Minh Tran ,  Minh Van Ngo ,  Hieu Pham ,  Erik Wilson ,  Robert Huertas

    IPC分类号： H01L21/31 ,  H01L21/469 ,  H01L23/58

    CPC分类号： H01L21/022 ,  H01L21/02348 ,  H01L21/76224 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76837

    摘要： During semiconductor fabrication homogeneous gap-filling is achieved by depositing a thin dielectric layer into the gap, post deposition curing, and then repeating deposition and post deposition curing until gap-filling is completed. Embodiments include depositing a layer of low deposition temperature gap-fill dielectric into a high aspect ratio opening, such as a shallow trench or a gap between closely spaced apart gate electrode structures, as at a thickness of about 10 Å to about 500 Å, curing after deposition, as by UV radiation or by heating at a temperature of about 400° C. to about 1000° C., depositing another layer of low deposition temperature gap-filled dielectric, and curing after deposition. Embodiments include separately depositing and separately curing multiple layers.

    摘要翻译： 在半导体制造期间，通过将薄介电层沉积到间隙中，后沉积固化，然后重复沉积和后沉积固化直到间隙填充完成来实现均匀间隙填充。 实施例包括将低沉积温度间隙填充电介质的层沉积到高纵横比开口中，例如浅沟槽或紧密间隔开的栅电极结构之间的间隙，其厚度约为至约500，固化 在沉积之后，如通过UV辐射或在约400℃至约1000℃的温度下加热，沉积另一层低沉积温度充满间隙的电介质，并在沉积后固化。 实施例包括分别沉积和分别固化多层。

    Method of forming a metal or metal nitride interface layer between silicon nitride and copper
    6.
    发明授权
    Method of forming a metal or metal nitride interface layer between silicon nitride and copper 有权
    在氮化硅和铜之间形成金属或金属氮化物界面层的方法

    公开(公告)号：US06518167B1

    公开(公告)日：2003-02-11

    申请号：US10123588

    申请日：2002-04-16

    申请人： Lu You ,  Matthew S. Buynoski ,  Paul R. Besser ,  Jeremias D. Romero ,  Pin-Chin Connie Wang ,  Minh Q. Tran

    发明人： Lu You ,  Matthew S. Buynoski ,  Paul R. Besser ,  Jeremias D. Romero ,  Pin-Chin Connie Wang ,  Minh Q. Tran

    IPC分类号： H01L214763

    CPC分类号： H01L21/76849 ,  H01L21/28562 ,  H01L21/76834

    摘要： A method of forming a metal or metal nitride layer interface between a copper layer and a silicon nitride layer can include providing a metal organic gas or metal/metal nitride precursor over a copper layer, forming a metal or metal nitride layer from reactions between the metal organic gas or metal/metal nitride precursor and the copper layer, and depositing a silicon nitride layer over the metal or metal nitride layer and copper layer. The metal or metal nitride layer can provide a better interface adhesion between the silicon nitride layer and the copper layer. The metal layer can improve the interface between the copper layer and the silicon nitride layer, improving electromigration reliability and, thus, integrated circuit device performance.

    摘要翻译： 在铜层和氮化硅层之间形成金属或金属氮化物层界面的方法可以包括在铜层上提供金属有机气体或金属/金属氮化物前体，从金属或金属氮化物层之间的反应形成金属或金属氮化物层 有机气体或金属/金属氮化物前体和铜层，以及在金属或金属氮化物层和铜层上沉积氮化硅层。 金属或金属氮化物层可以在氮化硅层和铜层之间提供更好的界面粘合性。 金属层可以改善铜层和氮化硅层之间的界面，提高电迁移可靠性，从而提高集成电路器件的性能。

    Use of ta/tan for preventing copper contamination of low-k dielectric layers
    7.
    发明授权
    Use of ta/tan for preventing copper contamination of low-k dielectric layers 有权
    使用ta / tan来防止低k电介质层的铜污染

    公开(公告)号：US06663787B1

    公开(公告)日：2003-12-16

    申请号：US09776747

    申请日：2001-02-06

    申请人： Lu You ,  Christy Woo ,  Pin Chin Connie Wang

    发明人： Lu You ,  Christy Woo ,  Pin Chin Connie Wang

    IPC分类号： H01L214763

    CPC分类号： H01L21/76844 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76813 ,  H01L21/76831 ,  H01L21/76838 ,  H01L21/76862 ,  H01L21/76865

    摘要： A semiconductor device includes a first metallization level, a first diffusion barrier layer, a first etch stop layer, a dielectric layer and an opening extending through the dielectric layer, the first etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization level. The first etch stop layer is disposed over the first diffusion barrier layer, and the dielectric layer is disposed over the first etch stop layer. The opening can also have rounded corners. A sidewall diffusion barrier layer can be disposed on sidewalls of the opening, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. The first etch stop layer can be formed from a material different than the first barrier layer, and the material of the first barrier layer can be selected from the group consisting of tantalum, titanium, tantalum nitride, titanium nitride, and tungsten nitride. Metal within the opening form a second metal feature, and the metal can comprise copper or a copper alloy. A method of manufacturing the semiconductor device is also disclosed.

    摘要翻译： 半导体器件包括第一金属化水平，第一扩散阻挡层，第一蚀刻停止层，电介质层和延伸穿过介电层的开口，第一蚀刻停止层和第一扩散阻挡层。 第一扩散阻挡层设置在第一金属化层上。 第一蚀刻停止层设置在第一扩散阻挡层上，并且电介质层设置在第一蚀刻停止层上。 开口也可以有圆角。 侧壁扩散阻挡层可以设置在开口的侧壁上，并且侧壁扩散阻挡层由与第一扩散阻挡层相同的材料形成。 第一蚀刻停止层可以由不同于第一阻挡层的材料形成，并且第一阻挡层的材料可以选自钽，钛，氮化钽，氮化钛和氮化钨。 开口内的金属形成第二金属特征，金属可以包括铜或铜合金。 还公开了制造半导体器件的方法。