公开(公告)号：US06663787B1

公开(公告)日：2003-12-16

申请号：US09776747

申请日：2001-02-06

申请人： Lu You ,  Christy Woo ,  Pin Chin Connie Wang

发明人： Lu You ,  Christy Woo ,  Pin Chin Connie Wang

IPC分类号： H01L214763

CPC分类号： H01L21/76844 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76813 ,  H01L21/76831 ,  H01L21/76838 ,  H01L21/76862 ,  H01L21/76865

摘要： A semiconductor device includes a first metallization level, a first diffusion barrier layer, a first etch stop layer, a dielectric layer and an opening extending through the dielectric layer, the first etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization level. The first etch stop layer is disposed over the first diffusion barrier layer, and the dielectric layer is disposed over the first etch stop layer. The opening can also have rounded corners. A sidewall diffusion barrier layer can be disposed on sidewalls of the opening, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. The first etch stop layer can be formed from a material different than the first barrier layer, and the material of the first barrier layer can be selected from the group consisting of tantalum, titanium, tantalum nitride, titanium nitride, and tungsten nitride. Metal within the opening form a second metal feature, and the metal can comprise copper or a copper alloy. A method of manufacturing the semiconductor device is also disclosed.

摘要翻译： 半导体器件包括第一金属化水平，第一扩散阻挡层，第一蚀刻停止层，电介质层和延伸穿过介电层的开口，第一蚀刻停止层和第一扩散阻挡层。 第一扩散阻挡层设置在第一金属化层上。 第一蚀刻停止层设置在第一扩散阻挡层上，并且电介质层设置在第一蚀刻停止层上。 开口也可以有圆角。 侧壁扩散阻挡层可以设置在开口的侧壁上，并且侧壁扩散阻挡层由与第一扩散阻挡层相同的材料形成。 第一蚀刻停止层可以由不同于第一阻挡层的材料形成，并且第一阻挡层的材料可以选自钽，钛，氮化钽，氮化钛和氮化钨。 开口内的金属形成第二金属特征，金属可以包括铜或铜合金。 还公开了制造半导体器件的方法。

公开(公告)号：US06518167B1

公开(公告)日：2003-02-11

申请号：US10123588

申请日：2002-04-16

申请人： Lu You ,  Matthew S. Buynoski ,  Paul R. Besser ,  Jeremias D. Romero ,  Pin-Chin Connie Wang ,  Minh Q. Tran

发明人： Lu You ,  Matthew S. Buynoski ,  Paul R. Besser ,  Jeremias D. Romero ,  Pin-Chin Connie Wang ,  Minh Q. Tran

IPC分类号： H01L214763

CPC分类号： H01L21/76849 ,  H01L21/28562 ,  H01L21/76834

摘要： A method of forming a metal or metal nitride layer interface between a copper layer and a silicon nitride layer can include providing a metal organic gas or metal/metal nitride precursor over a copper layer, forming a metal or metal nitride layer from reactions between the metal organic gas or metal/metal nitride precursor and the copper layer, and depositing a silicon nitride layer over the metal or metal nitride layer and copper layer. The metal or metal nitride layer can provide a better interface adhesion between the silicon nitride layer and the copper layer. The metal layer can improve the interface between the copper layer and the silicon nitride layer, improving electromigration reliability and, thus, integrated circuit device performance.

摘要翻译： 在铜层和氮化硅层之间形成金属或金属氮化物层界面的方法可以包括在铜层上提供金属有机气体或金属/金属氮化物前体，从金属或金属氮化物层之间的反应形成金属或金属氮化物层 有机气体或金属/金属氮化物前体和铜层，以及在金属或金属氮化物层和铜层上沉积氮化硅层。 金属或金属氮化物层可以在氮化硅层和铜层之间提供更好的界面粘合性。 金属层可以改善铜层和氮化硅层之间的界面，提高电迁移可靠性，从而提高集成电路器件的性能。

公开(公告)号：US07169706B2

公开(公告)日：2007-01-30

申请号：US10687186

申请日：2003-10-16

申请人： Sergey D. Lopatin ,  Paul R. Besser ,  Alline F. Myers ,  Jeremias D. Romero ,  Minh Q. Tran ,  Lu You ,  Pin-Chin Connie Wang

发明人： Sergey D. Lopatin ,  Paul R. Besser ,  Alline F. Myers ,  Jeremias D. Romero ,  Minh Q. Tran ,  Lu You ,  Pin-Chin Connie Wang

IPC分类号： H01L21/44

CPC分类号： H01L21/76846 ,  H01L21/76877

摘要： An exemplary embodiment is related to a method of using an adhesion precursor in an integrated circuit fabrication process. The method includes providing a gas of material over a dielectric material and providing a copper layer over an adhesion precursor layer. The adhesion precursor layer is formed by the gas, and the dielectric material includes an aperture.

摘要翻译： 示例性实施例涉及在集成电路制造工艺中使用粘附前体的方法。 该方法包括在介电材料上提供材料的气体并在粘附前体层上提供铜层。 粘附前体层由气体形成，电介质材料包括孔。

公开(公告)号：US06992004B1

公开(公告)日：2006-01-31

申请号：US10209060

申请日：2002-07-31

申请人： Paul R. Besser ,  Matthew S. Buynoski ,  Minh Q. Tran ,  Pin-Chin Connie Wang ,  Lu You ,  Sergey D. Lopatin ,  Jeremias D. Romero

发明人： Paul R. Besser ,  Matthew S. Buynoski ,  Minh Q. Tran ,  Pin-Chin Connie Wang ,  Lu You ,  Sergey D. Lopatin ,  Jeremias D. Romero

IPC分类号： H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/76801 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76859 ,  H01L21/76867

摘要： A method for manufacturing an integrated circuit having improved electromigration characteristics includes forming an aperture in an interlevel dielectric layer and providing a barrier layer in the aperture. The aperture is filled with a metal material and a barrier layer is provided above the metal material. An intermetallic region can be formed at an interface of the metal material and the barrier layer. The intermetallic material can be formed by implantation of species.

摘要翻译： 用于制造具有改善的电迁移特性的集成电路的方法包括在层间电介质层中形成孔，并在孔中提供阻挡层。 孔被金属材料填充，并且在金属材料上方设有阻挡层。 可以在金属材料和阻挡层的界面处形成金属间化合物区域。 金属间化合物可以通过种植物形成。

公开(公告)号：US06586842B1

公开(公告)日：2003-07-01

申请号：US09793993

申请日：2001-02-28

申请人： Lu You ,  Fei Wang ,  Christy Woo

发明人： Lu You ,  Fei Wang ,  Christy Woo

IPC分类号： H01L2352

CPC分类号： H01L21/76831 ,  H01L21/76804 ,  H01L21/76813 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a first metallization layer, a first diffusion barrier layer, a second etch stop layer, a first dielectric layer, a first etch stop layer, a second dielectric layer, a trench extending through the second dielectric layer and the first etch stop layer, and a via extending through the first dielectric layer, the second etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization layer. The second etch stop layer is disposed over and spaced from the first diffusion barrier layer, and the first dielectric layer is disposed over the second etch stop layer. The via can also have rounded corners. A third etch stop layer can also be disposed between the first diffusion barrier layer and the second etch stop layer. A sidewall diffusion barrier layer can be disposed on sidewalls of the via and trench, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. A method of manufacturing the semiconductor device is also disclosed.

摘要翻译： 半导体器件包括第一金属化层，第一扩散阻挡层，第二蚀刻停止层，第一介电层，第一蚀刻停止层，第二介电层，延伸穿过第二介电层的沟槽和第一蚀刻停止层 层，以及延伸穿过第一介电层，第二蚀刻停止层和第一扩散阻挡层的通孔。 第一扩散阻挡层设置在第一金属化层上。 第二蚀刻停止层设置在第一扩散阻挡层之上并与第一扩散阻挡层隔开，并且第一介电层设置在第二蚀刻停止层上。 通孔也可以有圆角。 第三蚀刻停止层也可以设置在第一扩散阻挡层和第二蚀刻停止层之间。 侧壁扩散阻挡层可以设置在通孔和沟槽的侧壁上，并且侧壁扩散阻挡层由与第一扩散阻挡层相同的材料形成。 还公开了制造半导体器件的方法。

公开(公告)号：US06939793B1

公开(公告)日：2005-09-06

申请号：US10422784

申请日：2003-04-25

申请人： Lu You ,  Fei Wang ,  Christy Woo

发明人： Lu You ,  Fei Wang ,  Christy Woo

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/4763

CPC分类号： H01L21/76831 ,  H01L21/76804 ,  H01L21/76813 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a first metallization layer, a first diffusion barrier layer, a second etch stop layer, a first dielectric layer, a first etch stop layer, a second dielectric layer, a trench extending through the second dielectric layer and the first etch stop layer, and a via extending through the first dielectric layer, the second etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization layer. The second etch stop layer is disposed over and spaced from the first diffusion barrier layer, and the first dielectric layer is disposed over the second etch stop layer. The via can also have rounded corners. A third etch stop layer can also be disposed between the first diffusion barrier layer and the second etch stop layer. A sidewall diffusion barrier layer can be disposed on sidewalls of the via and trench, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. A method of manufacturing the semiconductor device is also disclosed.

摘要翻译： 半导体器件包括第一金属化层，第一扩散阻挡层，第二蚀刻停止层，第一介电层，第一蚀刻停止层，第二介电层，延伸穿过第二介电层的沟槽和第一蚀刻停止层 层，以及延伸穿过第一介电层，第二蚀刻停止层和第一扩散阻挡层的通孔。 第一扩散阻挡层设置在第一金属化层上。 第二蚀刻停止层设置在第一扩散阻挡层之上并与第一扩散阻挡层隔开，并且第一介电层设置在第二蚀刻停止层上。 通孔也可以有圆角。 第三蚀刻停止层也可以设置在第一扩散阻挡层和第二蚀刻停止层之间。 侧壁扩散阻挡层可以设置在通孔和沟槽的侧壁上，并且侧壁扩散阻挡层由与第一扩散阻挡层相同的材料形成。 还公开了制造半导体器件的方法。

公开(公告)号：US08202810B2

公开(公告)日：2012-06-19

申请号：US11971331

申请日：2008-01-09

申请人： Alexander H. Nickel ,  Allen L. Evans ,  Minh Quoc Tran ,  Lu You ,  Minh Van Ngo ,  Pei-Yuan Gao ,  William S. Brennan ,  Erik Wilson ,  Sung Jin Kim ,  Hieu Trung Pham

发明人： Alexander H. Nickel ,  Allen L. Evans ,  Minh Quoc Tran ,  Lu You ,  Minh Van Ngo ,  Pei-Yuan Gao ,  William S. Brennan ,  Erik Wilson ,  Sung Jin Kim ,  Hieu Trung Pham

IPC分类号： H01L21/31

CPC分类号： H01L21/76877 ,  H01L21/76814 ,  H01L21/76828 ,  H01L21/76834 ,  H01L21/76883 ,  Y10S438/902

摘要： A method for forming a single damascene and/or dual damascene, contact and interconnect structure, comprising: performing front end processing, depositing copper including a copper barrier, annealing the copper in at least 90% N2 with less than 10% H2, performing planarization, performing in-situ low-H NH3 plasma treatment and low Si—H SiN etch stop layer deposition, and performing remaining back end processing.

摘要翻译： 一种用于形成单个镶嵌和/或双镶嵌，接触和互连结构的方法，包括：执行前端处理，沉积包含铜屏障的铜，在至少90％的N 2中以小于10％的H 2退火铜，进行平面化 ，进行原位低H NH 3等离子体处理和低Si-H SiN蚀刻停止层沉积，并执行剩余的后端处理。

公开(公告)号：US20080108193A1

公开(公告)日：2008-05-08

申请号：US11593086

申请日：2006-11-06

申请人： Lu You ,  Alexander Nickel ,  Minh Q. Tran ,  Minh-Van Ngo ,  Hieu Pham ,  Erik Wilson ,  Hirokazu Tokuno ,  Amir Hossein Jafarpour ,  Inkuk Kang ,  Robert Huertas

发明人： Lu You ,  Alexander Nickel ,  Minh Q. Tran ,  Minh-Van Ngo ,  Hieu Pham ,  Erik Wilson ,  Hirokazu Tokuno ,  Amir Hossein Jafarpour ,  Inkuk Kang ,  Robert Huertas

IPC分类号： H01L21/336 ,  H01L21/44

CPC分类号： H01L21/76883 ,  H01L27/11521

摘要： Data retention in flash memory devices, such as mirrorbit devices, is improved by reducing the generation and/or diffusion of hydrogen ions during back end processing, such as annealing inlaid Cu. Embodiments include annealing inlaid Cu in an N2 atmosphere containing low H2 or no H2, and at temperatures less than 200° C., e.g., 100° C. to 150° C.

摘要翻译： 通过减少后端处理中的氢离子的产生和/或扩散（例如退火的Cu）来改善闪存器件（例如镜像位装置）中的数据保留。 实施方案包括在含有低H 2 N 2或无H 2 N的N 2 O 2气氛中以及在低于200℃的温度下退火嵌入的Cu， 例如，100℃至150℃

公开(公告)号：US20080096364A1

公开(公告)日：2008-04-24

申请号：US11582442

申请日：2006-10-18

申请人： Erik Wilson ,  Minh-Van Ngo ,  Hieu Pham ,  Robert Huertas ,  Lu You ,  Hirokazu Tokuno ,  Alexander Nickel ,  Minh Tran

发明人： Erik Wilson ,  Minh-Van Ngo ,  Hieu Pham ,  Robert Huertas ,  Lu You ,  Hirokazu Tokuno ,  Alexander Nickel ,  Minh Tran

IPC分类号： H01L21/76

CPC分类号： H01L21/823468 ,  H01L21/76829 ,  H01L21/76837 ,  H01L21/823437

摘要： Gap filling between features which are closely spaced is significantly improved by initially depositing a thin conformal layer followed by depositing a layer of gap filling dielectric material. Embodiments include depositing a thin conformal layer of silicon nitride or silicon oxide, as by atomic layer deposition or pulsed layer deposition, into the gap between adjacent gate electrode structures such that it flows into undercut regions of dielectric spacers on side surfaces of the gate electrode structures, and then depositing a layer of BPSG or P-HDP oxide on the thin conformal layer into the gap. Embodiments further include depositing the layers at a temperature less than 430° C., as by depositing a P-HDP oxide after depositing the conformal liner when the gate electrode structures include a layer of nickel silicide.

摘要翻译： 通过初始沉积薄的共形层，然后沉积一层间隙填充电介质材料，密切间隔的特征之间的间隙填充显着改善。 实施例包括通过原子层沉积或脉冲层沉积将氮化硅或氧化硅的薄保形层沉积到相邻栅电极结构之间的间隙中，使得其流到栅电极结构的侧表面上的电介质间隔物的底切区域 ，然后在薄的共形层上沉积一层BPSG或P-HDP氧化物到间隙中。 实施例还包括在低于430℃的温度下沉积层，如通过在栅极电极结构包括硅化镍层沉积保形衬垫之后沉积P-HDP氧化物。

公开(公告)号：US07309650B1

公开(公告)日：2007-12-18

申请号：US11065388

申请日：2005-02-24

申请人： Connie Pin-Chin Wang ,  Lu You ,  Zoran Krivokapic ,  Paul Raymond Besser ,  Suzette Keefe Pangrle

发明人： Connie Pin-Chin Wang ,  Lu You ,  Zoran Krivokapic ,  Paul Raymond Besser ,  Suzette Keefe Pangrle

IPC分类号： H01L21/44

CPC分类号： H01L29/7833 ,  B82Y10/00 ,  H01L21/28273 ,  H01L29/42332

摘要： A memory device having a metal nanocrystal charge storage structure and a method for its manufacture. The memory device may be manufactured by forming a first oxide layer on the semiconductor substrate, then disposing a porous dielectric layer on the oxide layer and disposing a second oxide layer on the porous dielectric layer. A layer of electrically conductive material is formed on the second layer of dielectric material. An etch mask is formed on the electrically conductive material. The electrically conductive material and the underlying dielectric layers are anisotropically etched to form a dielectric structure on which a gate electrode is disposed. A metal layer is formed on the dielectric structure and the gate electrode and treated so that portions of the metal layer diffuse into the porous dielectric layer. Then the metal layer is removed.

摘要翻译： 一种具有金属纳米晶体电荷存储结构的存储器件及其制造方法。 存储器件可以通过在半导体衬底上形成第一氧化物层，然后在氧化物层上设置多孔介电层并在第二氧化物层上设置第二氧化物层来制造。 在第二介电材料层上形成一层导电材料。 在导电材料上形成蚀刻掩模。 导电材料和下面的介电层被各向异性地蚀刻以形成其上设置有栅电极的电介质结构。 在介电结构和栅电极上形成金属层，并处理金属层的一部分扩散到多孔介电层中。 然后去除金属层。