公开(公告)号：US12023290B2

公开(公告)日：2024-07-02

申请号：US17365184

申请日：2021-07-01

申请人： Shih-Chieh Hung

发明人： Shih-Chieh Hung

IPC分类号： A61H1/00 ,  A61G7/015 ,  A61H1/02 ,  A61G7/008 ,  A61G13/00

CPC分类号： A61H1/005 ,  A61H1/0244 ,  A61G7/008 ,  A61G7/015 ,  A61G13/009 ,  A61H2001/0248 ,  A61H2201/0107 ,  A61H2201/12 ,  A61H2201/163 ,  A61H2201/1676 ,  A61H2203/0456

摘要： A rehabilitation assisting apparatus has a main body, a waist assisting unit mounted above the main body, and two leg assisting units separately disposed side by side above the main body. Each of the leg assisting units is pivotally connected with the waist assisting unit. An upper rocking plate of the waist assisting unit can be driven to roll leftward and rightward to rehabilitate or train a waist of a user. A leg lifting bracket of each of the leg assisting unit can be driven to pitch upward and downward to rehabilitate or train a leg of the user.

公开(公告)号：US08900860B2

公开(公告)日：2014-12-02

申请号：US12627614

申请日：2009-11-30

申请人： Shih-Chieh Hung

发明人： Shih-Chieh Hung

IPC分类号： C12N5/07 ,  C12N5/10 ,  C12N5/071 ,  C12N5/00 ,  C12N5/02 ,  C12N5/0775

CPC分类号： C12N5/0663 ,  C12N2500/02

摘要： The present invention relates to a novel method for expanding mesenchymal stem cells (MSCs) in low-density and hypoxic condition as compared to normal air conditions traditionally used in cell culture. The present method provides rapid and efficient expansion of human MSCs without losing cellular proliferation and stem cell properties, including increase in proliferation, decrease in senescence, and increase in differentiation potential both in vitro and in vivo. The expanded MSCs by the present method may maintain normal karyotyping, and will not form tumor when transplanted into mammal.

摘要翻译： 本发明涉及与传统上用于细胞培养的正常空气条件相比，在低密度和低氧条件下扩展间充质干细胞（MSC）的新方法。 本发明方法提供人体MSC的快速和有效的扩增，而不会丧失细胞增殖和干细胞特性，包括体外和体内增殖，衰老减少和分化潜能的增加。 通过本方法扩增的MSC可保持正常的核型分析，并且在移植到哺乳动物中时不会形成肿瘤。

公开(公告)号：US08674673B2

公开(公告)日：2014-03-18

申请号：US13022571

申请日：2011-02-07

申请人： Shih-Chieh Hung ,  Hua-Chiang Huang ,  Jiun-Chiang Chen

发明人： Shih-Chieh Hung ,  Hua-Chiang Huang ,  Jiun-Chiang Chen

IPC分类号： G05F1/00

CPC分类号： H02M3/1588 ,  H02M2001/0032 ,  Y02B70/1466 ,  Y02B70/16

摘要： A switching power converter including an upper-bridge switch, a lower-bridge switch, an impedance circuit, a first control circuit, a second control circuit and a logic circuit is provided. The impedance circuit generates an output voltage and a sensing current according to a conductive state of the upper-bridge switch and the lower-bridge switch. The first control circuit generates a first pulse signal according to the output voltage. The second control circuit has a first mode and a second mode for generating a second pulse signal and a third pulse signal individually. Furthermore, the second control circuit uses different threshold values in different modes to determine whether to switch the mode thereof, so as to form a hysteretic effect in mode switching. The logic circuit controls the upper-bridge switch by the first pulse signal, and controls the lower-bridge switch by the second pulse signal or the third pulse signal.

摘要翻译： 提供一种包括上桥开关，下桥开关，阻抗电路，第一控制电路，第二控制电路和逻辑电路的开关电源转换器。 阻抗电路根据上桥开关和下桥开关的导通状态产生输出电压和感测电流。 第一控制电路根据输出电压产生第一脉冲信号。 第二控制电路具有分别产生第二脉冲信号和第三脉冲信号的第一模式和第二模式。 此外，第二控制电路使用不同模式的不同阈值来确定是否切换其模式，以便在模式切换中形成滞后效应。 逻辑电路通过第一脉冲信号控制上桥开关，并通过第二脉冲信号或第三脉冲信号控制下桥开关。

公开(公告)号：US20100289075A1

公开(公告)日：2010-11-18

申请号：US12536504

申请日：2009-08-06

申请人： Wei-Chieh Lin ,  Li-Cheng Lin ,  Hsin-Yu Hsu ,  Ho-Tai Chen ,  Jen-Hao Yeh ,  Guo-Liang Yang ,  Chia-Hui Chen ,  Shih-Chieh Hung

发明人： Wei-Chieh Lin ,  Li-Cheng Lin ,  Hsin-Yu Hsu ,  Ho-Tai Chen ,  Jen-Hao Yeh ,  Guo-Liang Yang ,  Chia-Hui Chen ,  Shih-Chieh Hung

IPC分类号： H01L27/06 ,  H01L21/8234 ,  H01L21/336

CPC分类号： H01L27/0629 ,  H01L29/8725

摘要： A semiconductor device having integrated MOSFET and Schottky diode includes a substrate having a MOSFET region and a Schottky diode region defined thereon; a plurality of first trenches formed in the MOSFET region; and a plurality of second trenches formed in the Schottky diode region. The first trenches respectively including a first insulating layer formed over the sidewalls and bottom of the first trench and a first conductive layer filling the first trench serve as a trenched gate of the trench MOSFET. The second trenches respectively include a second insulating layer formed over the sidewalls and bottom of the second trench and a second conductive layer filling the second trench. A depth and a width of the second trenches are larger than that of the first trenches; and a thickness of the second insulating layer is larger than that of the first insulating layer.

摘要翻译： 具有集成MOSFET和肖特基二极管的半导体器件包括其上限定有MOSFET区和肖特基二极管区的衬底; 形成在所述MOSFET区域中的多个第一沟槽; 以及形成在肖特基二极管区域中的多个第二沟槽。 分别包括形成在第一沟槽的侧壁和底部上的第一绝缘层的第一沟槽和填充第一沟槽的第一导电层用作沟槽MOSFET的沟槽栅极。 第二沟槽分别包括形成在第二沟槽的侧壁和底部上的第二绝缘层和填充第二沟槽的第二导电层。 第二沟槽的深度和宽度大于第一沟槽的深度和宽度; 并且所述第二绝缘层的厚度大于所述第一绝缘层的厚度。

公开(公告)号：US08049273B2

公开(公告)日：2011-11-01

申请号：US12371618

申请日：2009-02-15

申请人： Wei-Chieh Lin ,  Ho-Tai Chen ,  Li-Cheng Lin ,  Jen-Hao Yeh ,  Hsin-Yen Chiu ,  Hsin-Yu Hsu ,  Shih-Chieh Hung

发明人： Wei-Chieh Lin ,  Ho-Tai Chen ,  Li-Cheng Lin ,  Jen-Hao Yeh ,  Hsin-Yen Chiu ,  Hsin-Yu Hsu ,  Shih-Chieh Hung

IPC分类号： H01L26/66

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4916

摘要： A power semiconductor device includes a backside metal layer, a substrate formed on the backside metal layer, a semiconductor layer formed on the substrate, and a frontside metal layer. The semiconductor layer includes a first trench structure including a gate oxide layer formed around a first trench with poly-Si implant, a second trench structure including a gate oxide layer formed around a second trench with poly-Si implant, a p-base region formed between the first trench structure and the second trench structure, a plurality of n+ source region formed on the p-base region and between the first trench structure and the second trench structure, a dielectric layer formed on the first trench structure, the second trench structure, and the plurality of n+ source region. The frontside metal layer is formed on the semiconductor layer and filling gaps formed between the plurality of n+ source region on the p-base region.

摘要翻译： 功率半导体器件包括背面金属层，形成在背面金属层上的衬底，形成在衬底上的半导体层和前侧金属层。 半导体层包括第一沟槽结构，其包括围绕具有多晶硅注入的第一沟槽形成的栅极氧化层，第二沟槽结构，包括围绕具有多晶硅注入的第二沟槽形成的栅极氧化层，形成的p基区 在所述第一沟槽结构和所述第二沟槽结构之间形成有多个n +源极区，形成在所述p基区上以及所述第一沟槽结构和所述第二沟槽结构之间，形成在所述第一沟槽结构上的介电层，所述第二沟槽结构 ，以及多个n +源极区域。 前半导体金属层形成在半导体层上并填充形成在p基区上的多个n +源极区之间的间隙。

公开(公告)号：US20100117142A1

公开(公告)日：2010-05-13

申请号：US12371618

申请日：2009-02-15

申请人： Wei-Chieh Lin ,  Ho-Tai Chen ,  Li-Cheng Lin ,  Jen-Hao Yeh ,  Hsin-Yen Chiu ,  Hsin-Yu Hsu ,  Shih-Chieh Hung

发明人： Wei-Chieh Lin ,  Ho-Tai Chen ,  Li-Cheng Lin ,  Jen-Hao Yeh ,  Hsin-Yen Chiu ,  Hsin-Yu Hsu ,  Shih-Chieh Hung

IPC分类号： H01L29/772

CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4916

摘要： A power semiconductor device includes a backside metal layer, a substrate formed on the backside metal layer, a semiconductor layer formed on the substrate, and a frontside metal layer. The semiconductor layer includes a first trench structure including a gate oxide layer formed around a first trench with poly-Si implant, a second trench structure including a gate oxide layer formed around a second trench with poly-Si implant, a p-base region formed between the first trench structure and the second trench structure, a plurality of n+ source region formed on the p-base region and between the first trench structure and the second trench structure, a dielectric layer formed on the first trench structure, the second trench structure, and the plurality of n+ source region. The frontside metal layer is formed on the semiconductor layer and filling gaps formed between the plurality of n+ source region on the p-base region.

摘要翻译： 功率半导体器件包括背面金属层，形成在背面金属层上的衬底，形成在衬底上的半导体层和前侧金属层。 半导体层包括第一沟槽结构，其包括围绕具有多晶硅注入的第一沟槽形成的栅极氧化层，第二沟槽结构，包括围绕具有多晶硅注入的第二沟槽形成的栅极氧化层，形成的p基区 在所述第一沟槽结构和所述第二沟槽结构之间形成有多个n +源极区，形成在所述p基区上以及所述第一沟槽结构和所述第二沟槽结构之间，形成在所述第一沟槽结构上的介电层，所述第二沟槽结构 ，以及多个n +源极区域。 前半导体金属层形成在半导体层上并填充形成在p基区上的多个n +源极区之间的间隙。

公开(公告)号：US07682903B1

公开(公告)日：2010-03-23

申请号：US12334492

申请日：2008-12-14

申请人： Wei-Chieh Lin ,  Hsin-Yu Hsu ,  Hsin-Yen Chiu ,  Shih-Chieh Hung ,  Ho-Tai Chen ,  Jen-Hao Yeh ,  Li-Cheng Lin

发明人： Wei-Chieh Lin ,  Hsin-Yu Hsu ,  Hsin-Yen Chiu ,  Shih-Chieh Hung ,  Ho-Tai Chen ,  Jen-Hao Yeh ,  Li-Cheng Lin

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/26586 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/66734

摘要： A method of forming a power device includes providing a substrate, a semiconductor layer having at least a trench and being disposed on the substrate, a gate insulating layer covering the semiconductor layer, and a conductive material disposed in the trench, performing an ion implantation process to from a body layer, performing a tilted ion implantation process to from a heavy doped region, forming a first dielectric layer overall, performing a chemical mechanical polishing process until the body layer disposed under the heavy doped region is exposed to form source regions on the opposite sides of the trench, and forming a source trace directly covering the source regions disposed on the opposite sides of the trench.

摘要翻译： 一种形成功率器件的方法包括提供衬底，至少具有沟槽并设置在衬底上的半导体层，覆盖半导体层的栅极绝缘层和设置在沟槽中的导电材料，执行离子注入工艺 从体层进行倾斜的离子注入工艺，从重掺杂区域进行倾斜的离子注入工艺，整体形成第一介电层，进行化学机械抛光工艺，直到布置在重掺杂区域之下的体层露出，形成源区 并且形成直接覆盖设置在沟槽的相对侧上的源极区域的源极迹线。

公开(公告)号：US08241978B2

公开(公告)日：2012-08-14

申请号：US12536504

申请日：2009-08-06

申请人： Wei-Chieh Lin ,  Li-Cheng Lin ,  Hsin-Yu Hsu ,  Ho-Tai Chen ,  Jen-Hao Yeh ,  Guo-Liang Yang ,  Chia-Hui Chen ,  Shih-Chieh Hung

发明人： Wei-Chieh Lin ,  Li-Cheng Lin ,  Hsin-Yu Hsu ,  Ho-Tai Chen ,  Jen-Hao Yeh ,  Guo-Liang Yang ,  Chia-Hui Chen ,  Shih-Chieh Hung

IPC分类号： H01L27/06 ,  H01L21/336

CPC分类号： H01L27/0629 ,  H01L29/8725

摘要： A semiconductor device having integrated MOSFET and Schottky diode includes a substrate having a MOSFET region and a Schottky diode region defined thereon; a plurality of first trenches formed in the MOSFET region; and a plurality of second trenches formed in the Schottky diode region. The first trenches respectively including a first insulating layer formed over the sidewalls and bottom of the first trench and a first conductive layer filling the first trench serve as a trenched gate of the trench MOSFET. The second trenches respectively include a second insulating layer formed over the sidewalls and bottom of the second trench and a second conductive layer filling the second trench. A depth and a width of the second trenches are larger than that of the first trenches; and a thickness of the second insulating layer is larger than that of the first insulating layer.

摘要翻译： 具有集成MOSFET和肖特基二极管的半导体器件包括其上限定有MOSFET区和肖特基二极管区的衬底; 形成在所述MOSFET区域中的多个第一沟槽; 以及形成在肖特基二极管区域中的多个第二沟槽。 分别包括形成在第一沟槽的侧壁和底部上的第一绝缘层的第一沟槽和填充第一沟槽的第一导电层用作沟槽MOSFET的沟槽栅极。 第二沟槽分别包括形成在第二沟槽的侧壁和底部上的第二绝缘层和填充第二沟槽的第二导电层。 第二沟槽的深度和宽度大于第一沟槽的深度和宽度; 并且所述第二绝缘层的厚度大于所述第一绝缘层的厚度。

公开(公告)号：US20120126775A1

公开(公告)日：2012-05-24

申请号：US13022571

申请日：2011-02-07

申请人： Shih-Chieh Hung ,  Hua-Chiang Huang ,  Jiun-Chiang Chen

发明人： Shih-Chieh Hung ,  Hua-Chiang Huang ,  Jiun-Chiang Chen

IPC分类号： G05F1/10

CPC分类号： H02M3/1588 ,  H02M2001/0032 ,  Y02B70/1466 ,  Y02B70/16

摘要： A switching power converter including an upper-bridge switch, a lower-bridge switch, an impedance circuit, a first control circuit, a second control circuit and a logic circuit is provided. The impedance circuit generates an output voltage and a sensing current according to a conductive state of the upper-bridge switch and the lower-bridge switch. The first control circuit generates a first pulse signal according to the output voltage. The second control circuit has a first mode and a second mode for generating a second pulse signal and a third pulse signal individually. Furthermore, the second control circuit uses different threshold values in different modes to determine whether to switch the mode thereof, so as to form a hysteretic effect in mode switching. The logic circuit controls the upper-bridge switch by the first pulse signal, and controls the lower-bridge switch by the second pulse signal or the third pulse signal.

摘要翻译： 提供一种包括上桥开关，下桥开关，阻抗电路，第一控制电路，第二控制电路和逻辑电路的开关电源转换器。 阻抗电路根据上桥开关和下桥开关的导通状态产生输出电压和感测电流。 第一控制电路根据输出电压产生第一脉冲信号。 第二控制电路具有分别产生第二脉冲信号和第三脉冲信号的第一模式和第二模式。 此外，第二控制电路使用不同模式的不同阈值来确定是否切换其模式，以便在模式切换中形成滞后效应。 逻辑电路通过第一脉冲信号控制上桥开关，并通过第二脉冲信号或第三脉冲信号控制下桥开关。

公开(公告)号：US08168480B2

公开(公告)日：2012-05-01

申请号：US12563172

申请日：2009-09-21

申请人： Wei-Chieh Lin ,  Ho-Tai Chen ,  Jen-Hao Yeh ,  Li-Cheng Lin ,  Shih-Chieh Hung

发明人： Wei-Chieh Lin ,  Ho-Tai Chen ,  Jen-Hao Yeh ,  Li-Cheng Lin ,  Shih-Chieh Hung

IPC分类号： H01L21/332

CPC分类号： H01L29/7395 ,  H01L29/0834 ,  H01L29/66333

摘要： An integrated structure of an IGBT and a diode includes a plurality of doped cathode regions, and a method of forming the same is provided. The doped cathode regions are stacked in a semiconductor substrate, overlapping and contacting with each other. As compared with other doped cathode regions, the higher a doped cathode region is disposed, the larger implantation area the doped cathode region has. The doped cathode regions and the semiconductor substrate have different conductive types, and are applied as a cathode of the diode and a collector of the IGBT. The stacked doped cathode regions can increase the thinness of the cathode, and prevent the wafer from being overly thinned and broken.

摘要翻译： IGBT和二极管的集成结构包括多个掺杂的阴极区域，并且提供其形成方法。 掺杂阴极区域堆叠在半导体衬底中，彼此重叠并接触。 与其他掺杂阴极区域相比，掺杂阴极区域越高，掺杂阴极区域的注入面积越大。 掺杂阴极区域和半导体衬底具有不同的导电类型，并且被施加作为二极管的阴极和IGBT的集电极。 堆叠的掺杂阴极区域可以增加阴极的薄度，并且防止晶片过度变薄和破裂。