中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

16 records (took 0.018 seconds)

    Digital Oversampling Clock And Data Recovery Circuit
    1.
    发明申请
    Digital Oversampling Clock And Data Recovery Circuit 审中-公开

    公开(公告)号：US20190379524A1

    公开(公告)日：2019-12-12

    申请号：US16546691

    申请日：2019-08-21

    Applicant: Silicon Laboratories Inc.

    Inventor： Hua Beng Chan ,  Rex Wong Tak Ying ,  Ricky Setiawan ,  Obaida Mohammed Khaled Abu Hilal

    IPC: H04L7/033

    Abstract: In one aspect, an apparatus includes: a first time-to-data converter (TDC) to oversample a first duration of incoming data and hold the oversampled first duration during receipt of a second duration of the incoming data; a second TDC to oversample the second duration of the incoming data and hold the oversampled second duration during receipt of a third duration of the incoming data; a processing circuit coupled to the first and second TDCs, the processing circuit including a first filter to filter the oversampled first duration and the oversampled second duration and generate a control output therefrom; and a digitally controlled oscillator (DCO) coupled to the processing circuit to receive the control output and generate a recovery clock signal therefrom.

    Digital oversampling clock and data recovery circuit
    3.
    发明授权
    Digital oversampling clock and data recovery circuit 有权

    公开(公告)号：US10826677B2

    公开(公告)日：2020-11-03

    申请号：US16546691

    申请日：2019-08-21

    Applicant: Silicon Laboratories Inc.

    Inventor： Hua Beng Chan ,  Rex Wong Tak Ying ,  Ricky Setiawan ,  Obaida Mohammed Khaled Abu Hilal

    IPC: H04L7/033

    Abstract: In one aspect, an apparatus includes: a first time-to-data converter (TDC) to oversample a first duration of incoming data and hold the oversampled first duration during receipt of a second duration of the incoming data; a second TDC to oversample the second duration of the incoming data and hold the oversampled second duration during receipt of a third duration of the incoming data; a processing circuit coupled to the first and second TDCs, the processing circuit including a first filter to filter the oversampled first duration and the oversampled second duration and generate a control output therefrom; and a digitally controlled oscillator (DCO) coupled to the processing circuit to receive the control output and generate a recovery clock signal therefrom.

    Digital Oversampling Clock And Data Recovery Circuit
    4.
    发明申请
    Digital Oversampling Clock And Data Recovery Circuit 审中-公开

    公开(公告)号：US20180152280A1

    公开(公告)日：2018-05-31

    申请号：US15884650

    申请日：2018-01-31

    Applicant: Silicon Laboratories Inc.

    Inventor： Hua Beng Chan ,  Rex Wong Tak Ying ,  Ricky Setiawan ,  Obaida Mohammed Khaled Abu Hilal

    IPC: H04L7/00 ,  H04B10/61

    CPC classification number: H04L7/0331

    Abstract: In one aspect, an apparatus includes: a first time-to-data converter (TDC) to oversample a first duration of incoming data and hold the oversampled first duration during receipt of a second duration of the incoming data; a second TDC to oversample the second duration of the incoming data and hold the oversampled second duration during receipt of a third duration of the incoming data; a processing circuit coupled to the first and second TDCs, the processing circuit including a first filter to filter the oversampled first duration and the oversampled second duration and generate a control output therefrom; and a digitally controlled oscillator (DCO) coupled to the processing circuit to receive the control output and generate a recovery clock signal therefrom.

    Digital Oversampling Clock And Data Recovery Circuit
    5.
    发明申请
    Digital Oversampling Clock And Data Recovery Circuit 有权

    公开(公告)号：US20170366330A1

    公开(公告)日：2017-12-21

    申请号：US15182951

    申请日：2016-06-15

    Applicant: Silicon Laboratories Inc.

    Inventor： Hua Beng Chan ,  Rex Wong Tak Ying ,  Ricky Setiawan ,  Obaida Mohammed Khaled Abu Hilal

    IPC: H04L7/00 ,  H04B10/61

    CPC classification number: H04L7/0331

    Abstract: In one aspect, an apparatus includes: a first time-to-data converter (TDC) to oversample a first duration of incoming data and hold the oversampled first duration during receipt of a second duration of the incoming data; a second TDC to oversample the second duration of the incoming data and hold the oversampled second duration during receipt of a third duration of the incoming data; a processing circuit coupled to the first and second TDCs, the processing circuit including a first filter to filter the oversampled first duration and the oversampled second duration and generate a control output therefrom; and a digitally controlled oscillator (DCO) coupled to the processing circuit to receive the control output and generate a recovery clock signal therefrom.

    Digital oversampling clock and data recovery circuit
    7.
    发明授权
    Digital oversampling clock and data recovery circuit 有权

    公开(公告)号：US09923710B2

    公开(公告)日：2018-03-20

    申请号：US15182951

    申请日：2016-06-15

    Applicant: Silicon Laboratories Inc.

    Inventor： Hua Beng Chan ,  Rex Wong Tak Ying ,  Ricky Setiawan ,  Obaida Mohammed Khaled Abu Hilal

    IPC: H04L7/00 ,  H04B10/61

    CPC classification number: H04L7/0331

    Abstract: In one aspect, an apparatus includes: a first time-to-data converter (TDC) to oversample a first duration of incoming data and hold the oversampled first duration during receipt of a second duration of the incoming data; a second TDC to oversample the second duration of the incoming data and hold the oversampled second duration during receipt of a third duration of the incoming data; a processing circuit coupled to the first and second TDCs, the processing circuit including a first filter to filter the oversampled first duration and the oversampled second duration and generate a control output therefrom; and a digitally controlled oscillator (DCO) coupled to the processing circuit to receive the control output and generate a recovery clock signal therefrom.

    Apparatus for gain selection with compensation for parasitic elements and associated methods
    9.
    发明授权
    Apparatus for gain selection with compensation for parasitic elements and associated methods 有权
    用于增益选择的装置，用于补偿寄生元件和相关方法

    公开(公告)号：US09515671B1

    公开(公告)日：2016-12-06

    申请号：US14732701

    申请日：2015-06-06

    Applicant: Silicon Laboratories Inc.

    Inventor： Axel Thomsen ,  Alan L. Westwick ,  Ricky Setiawan ,  Rex Wong Tak Ying

    IPC: H03M1/00 ,  H03M1/06 ,  H03K5/003 ,  H03M1/66

    CPC classification number: H03M1/0607 ,  H03K5/003 ,  H03M1/00 ,  H03M1/002 ,  H03M1/0609 ,  H03M1/66 ,  H03M1/664 ,  H03M1/682 ,  H03M1/747 ,  H03M1/808

    Abstract: Apparatus and associated methods are disclosed for gain programming or selection with parasitic element compensation. In one exemplary embodiment, an apparatus includes a first circuit that has a first programmable gain, and includes a first set of components having parasitic elements. The apparatus also includes a second circuit that has a second programmable gain, and includes a second set of components having parasitic elements. The apparatus has a gain that is a product of the first and second programmable gains. A gain error because of the parasitic elements of the first and second sets of components is canceled by setting the first programmable gain as a reciprocal of the second programmable gain.

    Abstract translation: 公开了用于利用寄生元件补偿进行增益编程或选择的装置和相关方法。 在一个示例性实施例中，装置包括具有第一可编程增益的第一电路，并且包括具有寄生元件的第一组分量。 该装置还包括具有第二可编程增益的第二电路，并且包括具有寄生元件的第二组分量。 该装置具有作为第一和第二可编程增益的乘积的增益。 通过将第一可编程增益设置为第二可编程增益的倒数来消除由于第一和第二组分组的寄生元件引起的增益误差。

    Digital oversampling clock and data recovery circuit
    10.
    发明授权
    Digital oversampling clock and data recovery circuit 有权

    公开(公告)号：US10461920B2

    公开(公告)日：2019-10-29

    申请号：US15884650

    申请日：2018-01-31

    Applicant: Silicon Laboratories Inc.

    Inventor： Hua Beng Chan ,  Rex Wong Tak Ying ,  Ricky Setiawan ,  Obaida Mohammed Khaled Abu Hilal

    IPC: H04L7/00 ,  H04L7/033

    Abstract: In one aspect, an apparatus includes: a first time-to-data converter (TDC) to oversample a first duration of incoming data and hold the oversampled first duration during receipt of a second duration of the incoming data; a second TDC to oversample the second duration of the incoming data and hold the oversampled second duration during receipt of a third duration of the incoming data; a processing circuit coupled to the first and second TDCs, the processing circuit including a first filter to filter the oversampled first duration and the oversampled second duration and generate a control output therefrom; and a digitally controlled oscillator (DCO) coupled to the processing circuit to receive the control output and generate a recovery clock signal therefrom.

Patent Agency Ranking