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公开(公告)号:US20160233194A1
公开(公告)日:2016-08-11
申请号:US14986149
申请日:2015-12-31
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor: Lu-Yi Chen , Chang-Lun Lu , Shih-Ching Chen , Guang-Hwa Ma , Cheng-Hsu Hsiao
IPC: H01L25/065 , H01L25/00
CPC classification number: H01L25/105 , H01L21/6835 , H01L23/3128 , H01L23/5384 , H01L23/5385 , H01L23/5386 , H01L25/03 , H01L2221/68345 , H01L2224/16227 , H01L2224/16235 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/81005 , H01L2224/83005 , H01L2225/1035 , H01L2225/1058 , H01L2924/15311 , H01L2924/1533 , H01L2924/18161 , H01L2924/19103
Abstract: A package structure is provided, which includes: a dielectric layer having opposite first and second surfaces; a circuit sub-layer formed in the dielectric layer; an electronic element disposed on the first surface of the dielectric layer and electrically connected to the circuit sub-layer; a plurality of conductive posts formed on the first surface of the dielectric layer and electrically connected to the circuit sub-layer; and an encapsulant formed on the first surface of the dielectric layer and encapsulating the electronic element and the conductive posts. Upper surfaces of the conductive posts are exposed from the encapsulant so as to allow another electronic element to be disposed on the conductive posts and electrically connected to the circuit sub-layer through the conductive posts, thereby overcoming the conventional drawback that another electronic element can only be disposed on a lower side of a package structure and improving the functionality of the package structure.
Abstract translation: 提供一种封装结构,其包括:具有相反的第一和第二表面的电介质层; 形成在电介质层中的电路子层; 设置在电介质层的第一表面上并电连接到电路子层的电子元件; 形成在电介质层的第一表面上并电连接到电路子层的多个导电柱; 以及形成在电介质层的第一表面上并封装电子元件和导电柱的密封剂。 导电柱的上表面从密封剂露出,以允许另一个电子元件设置在导电柱上,并通过导电柱与电路子层电连接,从而克服了另一个电子元件只能 设置在封装结构的下侧,并改善封装结构的功能。
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公开(公告)号:US08895366B2
公开(公告)日:2014-11-25
申请号:US14190635
申请日:2014-02-26
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor: Wen-Home Huang , Wen-Tsung Tseng , Chang-Fu Lin , Ho-Yi Tsai , Cheng-Hsu Hsiao
CPC classification number: H01L21/561 , H01L23/3128 , H01L23/3142 , H01L29/0657 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H01L2924/10158 , H01L2924/15311 , H01L2924/3011 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
Abstract: A semiconductor package and a fabrication method thereof are disclosed. The fabrication method includes the steps of providing a semiconductor chip having an active surface and a non-active surface opposing to the active surface, roughening a peripheral portion of the non-active surface so as to divide the non-active surface into the peripheral portion formed with a roughened structure and a non-roughened central portion, mounting the semiconductor chip on a chip carrier via a plurality of solder bumps formed on the active surface, forming an encapsulant on the chip carrier to encapsulate the semiconductor chip. The roughened structure formed on the peripheral portion of the non-active surface of the semiconductor chip can reinforce the bonding between the semiconductor chip and the encapsulant, and the non-roughened central portion of the non-active surface of the semiconductor chip can maintain the structural strength of the semiconductor chip.
Abstract translation: 公开了半导体封装及其制造方法。 该制造方法包括以下步骤:提供具有与活性表面相对的活性表面和非活性表面的半导体芯片,粗糙化非活性表面的周边部分,以将非活性表面划分成周边部分 形成有粗糙结构和非粗糙化的中心部分,通过形成在有源表面上的多个焊料凸块将半导体芯片安装在芯片载体上,在芯片载体上形成密封剂以封装半导体芯片。 形成在半导体芯片的非活性表面的周边部分上的粗糙结构可以加强半导体芯片和密封剂之间的接合,并且半导体芯片的非活性表面的非粗糙化的中心部分可以保持 半导体芯片的结构强度。
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公开(公告)号:US20150054150A1
公开(公告)日:2015-02-26
申请号:US14085101
申请日:2013-11-20
Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
Inventor: Cheng-Hsu Hsiao , Lung-Yuan Wang
IPC: H01L23/00
CPC classification number: H01L25/105 , H01L21/561 , H01L23/49811 , H01L23/49833 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73265 , H01L2224/97 , H01L2225/0651 , H01L2225/06568 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2225/107 , H01L2924/00014 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/00012 , H01L2924/014 , H01L2224/83 , H01L2224/81 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: A method for fabricating a semiconductor package is disclosed, which includes: providing first and second packaging substrates, wherein a surface of the first packaging substrate has first conductive pads and first conductive posts formed on the first conductive pads, a surface of the second packaging substrate has second conductive pads and second conductive posts formed on the second conductive pads, and the surface of the second packaging substrate further has a semiconductor chip disposed thereon; disposing the first packaging substrate on the second packaging substrate in a manner that the first conductive posts correspond in position to and are electrically connected to the second conductive posts; and forming an encapsulant between the first and second packaging substrates for encapsulating the first and second conductive posts and the semiconductor chip, thereby effectively preventing solder bridging and increasing the product yield and reliability.
Abstract translation: 公开了一种制造半导体封装的方法,其包括:提供第一和第二封装基板,其中第一封装基板的表面具有形成在第一导电焊盘上的第一导电焊盘和第一导电柱,第二封装基板的表面 具有形成在第二导电焊盘上的第二导电焊盘和第二导电柱,并且第二封装衬底的表面还具有设置在其上的半导体芯片; 将所述第一包装基板设置在所述第二包装基板上,使得所述第一导电柱位于所述第二导电柱的位置并且与所述第二导电柱电连接; 以及在第一和第二封装基板之间形成密封剂,用于封装第一和第二导电柱和半导体芯片,从而有效地防止焊料桥接并提高产品的产率和可靠性。
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公开(公告)号:US10242972B2
公开(公告)日:2019-03-26
申请号:US14986149
申请日:2015-12-31
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor: Lu-Yi Chen , Chang-Lun Lu , Shih-Ching Chen , Guang-Hwa Ma , Cheng-Hsu Hsiao
IPC: H01L23/58 , H01L21/78 , H01L25/10 , H01L21/683 , H01L23/538 , H01L23/31 , H01L25/03
Abstract: A package structure is provided, which includes: a dielectric layer having opposite first and second surfaces; a circuit sub-layer formed in the dielectric layer; an electronic element disposed on the first surface of the dielectric layer and electrically connected to the circuit sub-layer; a plurality of conductive posts formed on the first surface of the dielectric layer and electrically connected to the circuit sub-layer; and an encapsulant formed on the first surface of the dielectric layer and encapsulating the electronic element and the conductive posts. Upper surfaces of the conductive posts are exposed from the encapsulant so as to allow another electronic element to be disposed on the conductive posts and electrically connected to the circuit sub-layer through the conductive posts, thereby overcoming the conventional drawback that another electronic element can only be disposed on a lower side of a package structure and improving the functionality of the package structure.
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公开(公告)号:US20140179067A1
公开(公告)日:2014-06-26
申请号:US14190635
申请日:2014-02-26
Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
Inventor: Wen-Home Huang , Wen-Tsung Tseng , Chang-Fu Lin , Ho-Yi Tsai , Cheng-Hsu Hsiao
IPC: H01L21/56
CPC classification number: H01L21/561 , H01L23/3128 , H01L23/3142 , H01L29/0657 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H01L2924/10158 , H01L2924/15311 , H01L2924/3011 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
Abstract: A semiconductor package and a fabrication method thereof are disclosed. The fabrication method includes the steps of providing a semiconductor chip having an active surface and a non-active surface opposing to the active surface, roughening a peripheral portion of the non-active surface so as to divide the non-active surface into the peripheral portion formed with a roughened structure and a non-roughened central portion, mounting the semiconductor chip on a chip carrier via a plurality of solder bumps formed on the active surface, forming an encapsulant on the chip carrier to encapsulate the semiconductor chip. The roughened structure formed on the peripheral portion of the non-active surface of the semiconductor chip can reinforce the bonding between the semiconductor chip and the encapsulant, and the non-roughened central portion of the non-active surface of the semiconductor chip can maintain the structural strength of the semiconductor chip.
Abstract translation: 公开了半导体封装及其制造方法。 该制造方法包括以下步骤:提供具有与活性表面相对的活性表面和非活性表面的半导体芯片,粗糙化非活性表面的周边部分,以将非活性表面划分成周边部分 形成有粗糙结构和非粗糙化的中心部分,通过形成在有源表面上的多个焊料凸块将半导体芯片安装在芯片载体上,在芯片载体上形成密封剂以封装半导体芯片。 形成在半导体芯片的非活性表面的周边部分上的粗糙结构可以加强半导体芯片和密封剂之间的接合,并且半导体芯片的非活性表面的非粗糙化的中心部分可以保持 半导体芯片的结构强度。
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