公开(公告)号：US09899308B2

公开(公告)日：2018-02-20

申请号：US15434599

申请日：2017-02-16

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Wen-Tsung Tseng ,  Yi-Che Lai ,  Shih-Kuang Chiu ,  Mao-Hua Yeh

IPC: H01L21/48 ,  H01L23/13 ,  H01L23/14 ,  H01L23/373 ,  H01L23/498

CPC classification number: H01L23/49827 ,  H01L21/481 ,  H01L21/4853 ,  H01L23/13 ,  H01L23/147 ,  H01L23/15 ,  H01L23/3738 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L2224/11

Abstract: A semiconductor package is provided, including a semiconductor substrate having a plurality of conductive vias, a buffer layer formed on the semiconductor substrate, a plurality of conductive pads formed on end surfaces of the conductive vias and covering the buffer layer. During a reflow process, the buffer layer greatly reduces the thermal stress, thereby eliminating the occurrence of cracking at the interface of conductive pads. A method of fabricating such a semiconductor package is also provided.

公开(公告)号：US20170311445A1

公开(公告)日：2017-10-26

申请号：US15226996

申请日：2016-08-03

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hung-Hsien Chang ,  Jyun-Ling Tsai ,  Yu-Ling Yeh ,  Wen-Tsung Tseng ,  Yi-Che Lai

IPC: H05K1/14 ,  H05K1/11

CPC classification number: H05K1/144 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/16227 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83385 ,  H01L2224/92125 ,  H01L2924/10155 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2924/35121 ,  H05K1/11 ,  H05K3/284 ,  H05K2201/09036 ,  H05K2201/10378 ,  H05K2201/10977 ,  H05K2201/2072 ,  H01L2924/00012

Abstract: A substrate structure is provided, which includes a substrate having a plurality of conductors and at least a receiving space formed on a surface of the substrate with the receiving space free from penetrating the substrate. During an encapsulating process, an encapsulant can be filled in the receiving space so as to strengthen the bonding between the substrate and the encapsulant, thereby preventing delamination from occurring therebetween.

公开(公告)号：US20140127838A1

公开(公告)日：2014-05-08

申请号：US13845698

申请日：2013-03-18

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Pin-Cheng Huang ,  Chun-Tang Lin ,  Wen-Tsung Tseng ,  Yi-Che Lai

IPC: H01L21/66

CPC classification number: H01L22/14 ,  H01L21/6836 ,  H01L22/20 ,  H01L23/147 ,  H01L23/367 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0655 ,  H01L2221/68331 ,  H01L2221/68381 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/83005 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/16195 ,  H01L2924/351 ,  H01L2924/37001 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/81

Abstract: A method of testing a semiconductor package is provided, including: disposing at least an interposer on a top surface of an adhesive layer, the interposer having a first surface and a second surface opposite to the first surface, a plurality of conductive elements disposed between the second surface of the interposer and the adhesive layer; disposing at least a semiconductor chip on the first surface of the interposer, and performing an electrical test on the semiconductor chip via the conductive elements, wherein if there are a plurality of semiconductor chips that are disposed on the first surface of the interposer, the step of disposing the semiconductor chip and performing the electrical test on the semiconductor chip is iterated; and removing the adhesive layer. By using the method, the fabrication cost and equipment cost of the semiconductor package are reduced, and product yield is increased.

Abstract translation: 提供了一种测试半导体封装的方法，包括：至少在粘合剂层的顶表面上设置插入件，所述插入件具有第一表面和与第一表面相对的第二表面，多个导电元件设置在第二表面之间 插入器的第二表面和粘合剂层; 在所述插入件的第一表面上设置至少一个半导体芯片，并且经由所述导电元件对所述半导体芯片进行电测试，其中如果存在设置在所述插入件的第一表面上的多个半导体芯片，则所述步骤 重复设置半导体芯片并对半导体芯片进行电气测试; 并去除粘合剂层。 通过使用该方法，半导体封装的制造成本和设备成本降低，产品产量增加。

公开(公告)号：US10049975B2

公开(公告)日：2018-08-14

申请号：US15258303

申请日：2016-09-07

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Fang-Yu Liang ,  Hung-Hsien Chang ,  Yi-Che Lai ,  Wen-Tsung Tseng ,  Chen-Yu Huang

IPC: H05K7/10 ,  H05K7/12 ,  H01L23/498 ,  H01L23/00

Abstract: A substrate structure is provided, including a substrate body having a conductive pad, an insulation layer formed on the substrate body and exposing the conductive pad, a conductive pillar disposed on the conductive pad, and a metal pad disposed on the insulation layer and electrically connected to the conductive pillar. A conductive component can be coupled to the metal pad. During a high-temperature process, the conductive pillar and the metal pad disperse the remaining stress generated due to heat, thereby preventing the conductive component from being cracked.

公开(公告)号：US08987012B2

公开(公告)日：2015-03-24

申请号：US13845698

申请日：2013-03-18

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Pin-Cheng Huang ,  Chun-Tang Lin ,  Wen-Tsung Tseng ,  Yi-Che Lai

IPC: H01L21/66

CPC classification number: H01L22/14 ,  H01L21/6836 ,  H01L22/20 ,  H01L23/147 ,  H01L23/367 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0655 ,  H01L2221/68331 ,  H01L2221/68381 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/83005 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/16195 ,  H01L2924/351 ,  H01L2924/37001 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/81

Abstract: A method of testing a semiconductor package is provided, including: disposing at least an interposer on a top surface of an adhesive layer, the interposer having a first surface and a second surface opposite to the first surface, a plurality of conductive elements disposed between the second surface of the interposer and the adhesive layer; disposing at least a semiconductor chip on the first surface of the interposer, and performing an electrical test on the semiconductor chip via the conductive elements, wherein if there are a plurality of semiconductor chips that are disposed on the first surface of the interposer, the step of disposing the semiconductor chip and performing the electrical test on the semiconductor chip is iterated; and removing the adhesive layer. By using the method, the fabrication cost and equipment cost of the semiconductor package are reduced, and product yield is increased.

Abstract translation: 提供了一种测试半导体封装的方法，包括：至少在粘合剂层的顶表面上设置插入件，所述插入件具有第一表面和与第一表面相对的第二表面，多个导电元件设置在第二表面之间 插入器的第二表面和粘合剂层; 在所述插入件的第一表面上设置至少一个半导体芯片，并且经由所述导电元件对所述半导体芯片进行电测试，其中如果存在设置在所述插入件的第一表面上的多个半导体芯片，则所述步骤 重复设置半导体芯片并对半导体芯片进行电气测试; 并去除粘合剂层。 通过使用该方法，半导体封装的制造成本和设备成本降低，产品产量增加。

公开(公告)号：US20150069628A1

公开(公告)日：2015-03-12

申请号：US14259629

申请日：2014-04-23

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Wen-Tsung Tseng ,  Yi-Che Lai ,  Shih-Kuang Chiu ,  Mao-Hua Yeh

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L23/49827 ,  H01L21/481 ,  H01L21/4853 ,  H01L23/13 ,  H01L23/147 ,  H01L23/15 ,  H01L23/3738 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L2224/11

Abstract: A semiconductor package is provided, including a semiconductor substrate having a plurality of conductive vias, a buffer layer formed on the semiconductor substrate, a plurality of conductive pads formed on end surfaces of the conductive vias and covering the buffer layer. During a reflow process, the buffer layer greatly reduces the thermal stress, thereby eliminating the occurance of cracking at the interface of conductive pads. A method of fabricating such a semiconductor package is also provided.

Abstract translation: 提供一种半导体封装，包括具有多个导电通孔的半导体衬底，形成在半导体衬底上的缓冲层，形成在导电通孔的端表面上并覆盖缓冲层的多个导电焊盘。 在回流过程中，缓冲层大大降低了热应力，从而消除了导电焊盘界面处的开裂现象。 还提供了一种制造这种半导体封装的方法。

公开(公告)号：US20170229387A1

公开(公告)日：2017-08-10

申请号：US15434599

申请日：2017-02-16

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Wen-Tsung Tseng ,  Yi-Che Lai ,  Shih-Kuang Chiu ,  Mao-Hua Yeh

IPC: H01L23/498 ,  H01L23/13 ,  H01L23/14 ,  H01L21/48 ,  H01L23/373

CPC classification number: H01L23/49827 ,  H01L21/481 ,  H01L21/4853 ,  H01L23/13 ,  H01L23/147 ,  H01L23/15 ,  H01L23/3738 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L2224/11

Abstract: A semiconductor package is provided, including a semiconductor substrate having a plurality of conductive vias, a buffer layer formed on the semiconductor substrate, a plurality of conductive pads formed on end surfaces of the conductive vias and covering the buffer layer. During a reflow process, the buffer layer greatly reduces the thermal stress, thereby eliminating the occurance of cracking at the interface of conductive pads. A method of fabricating such a semiconductor package is also provided.

公开(公告)号：US20170229386A1

公开(公告)日：2017-08-10

申请号：US15258303

申请日：2016-09-07

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Fang-Yu Liang ,  Hung-Hsien Chang ,  Yi-Che Lai ,  Wen-Tsung Tseng ,  Chen-Yu Huang

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/562 ,  H01L2224/73204 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A substrate structure is provided, including a substrate body having a conductive pad, an insulation layer formed on the substrate body and exposing the conductive pad, a conductive pillar disposed on the conductive pad, and a metal pad disposed on the insulation layer and electrically connected to the conductive pillar. A conductive component can be coupled to the metal pad. During a high-temperature process, the conductive pillar and the metal pad disperse the remaining stress generated due to heat, thereby preventing the conductive component from being cracked.

公开(公告)号：US09607939B2

公开(公告)日：2017-03-28

申请号：US14259629

申请日：2014-04-23

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Wen-Tsung Tseng ,  Yi-Che Lai ,  Shih-Kuang Chiu ,  Mao-Hua Yeh

IPC: H01L21/768 ,  H01L23/498 ,  H01L23/14 ,  H01L23/15

CPC classification number: H01L23/49827 ,  H01L21/481 ,  H01L21/4853 ,  H01L23/13 ,  H01L23/147 ,  H01L23/15 ,  H01L23/3738 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L2224/11

Abstract: A semiconductor package is provided, including a semiconductor substrate having a plurality of conductive vias, a buffer layer formed on the semiconductor substrate, a plurality of conductive pads formed on end surfaces of the conductive vias and covering the buffer layer. During a reflow process, the buffer layer greatly reduces the thermal stress, thereby eliminating the occurance of cracking at the interface of conductive pads. A method of fabricating such a semiconductor package is also provided.

公开(公告)号：US20150035164A1

公开(公告)日：2015-02-05

申请号：US14012447

申请日：2013-08-28

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Guang-Hwa Ma ,  Shih-Kuang Chiu ,  Shih-Ching Chen ,  Chun-Chi Ke ,  Chang-Lun Lu ,  Chun-Hung Lu ,  Hsien-Wen Chen ,  Chun-Tang Lin ,  Yi-Che Lai ,  Chi-Hsin Chiu ,  Wen-Tsung Tseng ,  Tsung-Te Yuan ,  Lu-Yi Chen ,  Mao-Hua Yeh

IPC: H01L23/538 ,  H01L23/00

CPC classification number: H01L24/96 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3135 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/82005 ,  H01L2224/82007 ,  H01L2924/12042 ,  H01L2924/18162 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00

Abstract: The present invention provides a semiconductor package and a method of fabricating the same, including: placing in a groove of a carrier a semiconductor element having opposing active and non-active surfaces, and side surfaces abutting the active surface and the non-active surface; applying an adhesive material in the groove and around a periphery of the side surfaces of the semiconductor element; forming a dielectric layer on the adhesive material and the active surface of the semiconductor element; forming on the dielectric layer a circuit layer electrically connected to the semiconductor element; and removing a first portion of the carrier below the groove to keep a second portion of the carrier on a side wall of the groove intact for the second portion to function as a supporting member. The present invention does not require formation of a silicon interposer, and therefore the overall cost of a final product is much reduced.

Abstract translation: 本发明提供一种半导体封装及其制造方法，包括：将具有相对的有源和非有源表面的半导体元件和邻接有源表面和非有效表面的侧表面放置在载体的沟槽中; 在所述凹槽中并且围绕所述半导体元件的侧表面的周边施加粘合剂材料; 在所述粘合剂材料和所述半导体元件的有源表面上形成介电层; 在所述电介质层上形成电连接到所述半导体元件的电路层; 以及在所述凹槽下方移除所述载体的第一部分，以将所述载体的第二部分保持在所述凹槽的侧壁上，以使所述第二部分用作支撑构件。 本发明不需要形成硅插入件，因此最终产品的总成本大大降低。