公开(公告)号：US07685451B2

公开(公告)日：2010-03-23

申请号：US10327441

申请日：2002-12-20

Applicant: James S. Burns ,  Kenneth D. Shoemaker ,  Sudarshan Kumar ,  Tom E. Wang ,  David J. Ayers ,  Vivek Tiwari

Inventor： James S. Burns ,  Kenneth D. Shoemaker ,  Sudarshan Kumar ,  Tom E. Wang ,  David J. Ayers ,  Vivek Tiwari

IPC: G06F1/26

CPC classification number: G06F1/305

Abstract: A method and apparatus for compensating for current-change induced voltage changes is disclosed. In one embodiment, a digital throttle unit coupled to an instruction pipeline may generate a compensating current signal, which may then cause a dummy load to consume a compensating current. In another embodiment, a counter responsive to changes in clock frequency may generate a ramp current signal, which may then cause a dummy load to consume a current corresponding to the ramp current signal.

Abstract translation: 公开了一种用于补偿电流变化感应电压变化的方法和装置。 在一个实施例中，耦合到指令流水线的数字节流单元可以生成补偿电流信号，然后可以使虚拟负载消耗补偿电流。 在另一个实施例中，响应于时钟频率变化的计数器可产生斜坡电流信号，然后可以使虚拟负载消耗对应于斜坡电流信号的电流。

公开(公告)号：US06707318B2

公开(公告)日：2004-03-16

申请号：US10107740

申请日：2002-03-26

Applicant: Sudarshan Kumar ,  Shahram Jamshidi

Inventor： Sudarshan Kumar ,  Shahram Jamshidi

IPC: H03K19096

CPC classification number: H03K3/356173 ,  H03K3/012 ,  H03K19/0963

Abstract: An entry latch to provide a dynamic signal at an output port in response to input static signals at a pulldown network, the pulldown network to conditionally discharge an internal node depending upon the input static signals, the entry latch comprising a pass transistor having a first source/drain connected to the output port and a second source/drain connected to a gate of a pullup pMOSFET, where the pullup pMOSFET turns ON only if the pulldown network does not turn ON during the evaluation phase.

Abstract translation: 输入锁存器，用于响应于下拉网络处的输入静态信号在输出端口处提供动态信号，所述下拉网络根据输入的静态信号来有条件地排放内部节点，所述输入锁存器包括具有第一源的传输晶体管 /漏极连接到输出端口，第二个源极/漏极连接到上拉pMOSFET的栅极，其中只有在评估阶段下拉网络未导通时，上拉电阻pOSOSFET才会导通。

公开(公告)号：US06292029B1

公开(公告)日：2001-09-18

申请号：US09471650

申请日：1999-12-23

Applicant: Sudarshan Kumar ,  Wenjie Jiang

Inventor： Sudarshan Kumar ,  Wenjie Jiang

IPC: H03K19096

CPC classification number: H03K19/00338 ,  H03K19/096

Abstract: A technique for reducing soft errors in a dynamic circuit. For one embodiment, a dynamic circuit includes a dynamic logic gate having an output node at which a logical output value of the logic gate is detected. A keeper circuit coupled to the output node is configured to harden the dynamic circuit by increasing the critical charge at the output node.

公开(公告)号：US6124737A

公开(公告)日：2000-09-26

申请号：US345972

申请日：1999-06-30

Applicant: Jiann-Cherng James Lan ,  Sudarshan Kumar ,  Kamal J. Koshy

Inventor： Jiann-Cherng James Lan ,  Sudarshan Kumar ,  Kamal J. Koshy

IPC: H03K19/00 ,  H03K19/0185 ,  H03K19/0948

CPC classification number: H03K19/0016 ,  H03K19/01855

Abstract: A clock buffer includes a clocked pull-up transistor and a clocked pull-down transistor. The clocked pull-up transistor has a drain coupled to an output line and a gate coupled to a clock signal line. The clocked pull-down transistor includes a drain coupled to the output line, a gate coupled to the clock signal line, and having a width Y. The buffer further includes a first pull-down transistor having a drain coupled to a source of the clocked pull-down transistor, a gate coupled to a first input signal line, and having a width that is at least 10% greater than Y. This clock buffer provides reduced power consumption in comparison to a more conventional clock buffer.

Abstract translation: 时钟缓冲器包括时钟上拉晶体管和时钟控制下拉晶体管。 时钟上拉晶体管具有耦合到输出线的漏极和耦合到时钟信号线的栅极。 时钟控制的下拉晶体管包括耦合到输出线的漏极，耦合到时钟信号线的栅极并具有宽度Y.该缓冲器还包括第一下拉晶体管，其具有耦合到时钟信号源的漏极 下拉晶体管，耦合到第一输入信号线的栅极，并且具有比Y大至少10％的宽度。与较传统的时钟缓冲器相比，该时钟缓冲器提供了降低的功耗。

公开(公告)号：US5579254A

公开(公告)日：1996-11-26

申请号：US471287

申请日：1995-06-06

Applicant: Sudarshan Kumar ,  Jashojiban Banik

Inventor： Sudarshan Kumar ,  Jashojiban Banik

IPC: G06F7/50 ,  G06F7/506 ,  G06F7/38

CPC classification number: G06F7/506 ,  G06F7/507

Abstract: An N-bit conditional sum adder comprised of a number of 2-bit adders coupled in series. The 2-bit adders have a sum generation circuit which computes two sum bits from two 2-bit inputs. Each sum bit is processed by a maximum of two multiplexers in series for factoring any carry-ins from preceding 2-bit adders, regardless of the total number of N bits to be added. A carry generation circuit generates two carry signals. The appropriate carry signal is selected for propagation by a multiplexer comprised of a number of p-n passgates. The two carry signals plus their complements are first buffered before being input to the multiplexer. The multiplexer outputs the appropriate carry signal and its complement to be input to a succeeding 2-bit adder and for controlling a succeeding multiplexer selection.

公开(公告)号：US20120057135A1

公开(公告)日：2012-03-08

申请号：US12801468

申请日：2010-09-07

Applicant: Sudarshan Kumar

Inventor： Sudarshan Kumar

IPC: G03B21/14

CPC classification number: H04N9/3111

Abstract: A system comprising of low cost and low power projection engine comprising of means of producing non-coherent light source, means of condensing non-coherent light into narrow beams, means of focusing and scanning narrow beam light on screen where as image is projected on screen by producing light for each pixel of image. Source of non-coherent light can be LED.

Abstract translation: 一种包括低成本和低功率投影引擎的系统，包括产生非相干光源的装置，将非相干光聚焦成窄光束的装置，在屏幕上聚焦和扫描窄光束的装置，其中图像被投影在屏幕上 通过为图像的每个像素产生光。 非相干光源可以是LED。

公开(公告)号：US06593776B2

公开(公告)日：2003-07-15

申请号：US09922434

申请日：2001-08-03

Applicant: Sudarshan Kumar ,  Gaurav Mehta ,  Vivek Joshi

Inventor： Sudarshan Kumar ,  Gaurav Mehta ,  Vivek Joshi

IPC: H03K1994

CPC classification number: G11C8/10

Abstract: A decoder includes multiple decode gates, each to provide one bit of a decoded output signal. At least two of the decode gates share a transistor. According to one aspect, each of the multiple decode gates is a skewed gate.

Abstract translation: 解码器包括多个解码门，每个解码门提供解码输出信号的一位。 至少两个解码门共享晶体管。 根据一个方面，多个解码门中的每一个是偏斜门。

公开(公告)号：US6111435A

公开(公告)日：2000-08-29

申请号：US343961

申请日：1999-06-30

Applicant: Jiann-Cherng James Lan ,  Mahadevamurty Nemani ,  Narsing K. Vijayrao ,  Wenjie Jiang ,  Sudarshan Kumar

Inventor： Jiann-Cherng James Lan ,  Mahadevamurty Nemani ,  Narsing K. Vijayrao ,  Wenjie Jiang ,  Sudarshan Kumar

IPC: H03K17/693 ,  H03K19/173 ,  H03K19/20

CPC classification number: H03K17/693 ,  H03K19/1731

Abstract: A circuit includes first and second pull-up transistors having first and second drains, respectively, each coupled to separate voltage clamps. The gates of each of the two pull-up transistors are coupled to a clock signal line. The circuit further includes a shared pull-down transistor, the gate of which is coupled to the clock signal line. The drain of the shared pull-down transistor is coupled to the first drain via at least one pull-down transistor in series with the shared pull-down transistor. The drain of the shared pull-down transistor is also coupled to the second drain via at least one pull-down transistor in series with the shared pull-down transistor. This circuit may be found useful in multiplexing applications.

Abstract translation: 电路包括第一和第二上拉晶体管，其分别具有分别耦合到单独的电压钳位的第一和第二漏极。 两个上拉晶体管中的每一个的栅极耦合到时钟信号线。 电路还包括共享下拉晶体管，其栅极耦合到时钟信号线。 共享下拉晶体管的漏极经由与共用下拉晶体管串联的至少一个下拉晶体管耦合到第一漏极。 共享下拉晶体管的漏极还通过与共享下拉晶体管串联的至少一个下拉晶体管耦合到第二漏极。 该电路可用于多路复用应用。

公开(公告)号：US6058403A

公开(公告)日：2000-05-02

申请号：US130379

申请日：1998-08-06

Applicant: Narsing K. Vijayrao ,  Sudarshan Kumar

Inventor： Narsing K. Vijayrao ,  Sudarshan Kumar

IPC: H03K19/096 ,  G06F7/74 ,  G06F7/00

CPC classification number: G06F7/74

Abstract: A broken stack domino priority encoder to provide a set of voltages to uniquely identify the position of a leading one or leading zero in a binary word, the domino priority encoder comprising a by-pass stack of nMOSFETs and a broken stack of nMOSFETs to discharge various nodes. The stack depth of nMOSFETs between each node and ground is minimized in order to maximize switching speed of the priority encoder.

Abstract translation: 一种破碎的堆叠多米诺骨牌优先编码器，用于提供一组电压以唯一地识别二进制字中的前导或前导零的位置，多米诺骨牌优先级编码器包括nMOSFET的旁路堆叠和破坏的nMOSFET堆叠，以排放各种 节点。 为了最大化优先编码器的切换速度，使每个节点和地之间的nMOSFET的堆叠深度最小化。

公开(公告)号：US5608741A

公开(公告)日：1997-03-04

申请号：US156427

申请日：1993-11-23

Applicant: Sudarshan Kumar ,  Shyue L. Kuo ,  Chung Y. Yip

Inventor： Sudarshan Kumar ,  Shyue L. Kuo ,  Chung Y. Yip

IPC: G06F11/10

CPC classification number: G06F11/10

Abstract: The present invention discloses a fast parity bit generator using 4-bit XOR cells implemented using complement pass-transistor logic. For 2.sup.2n inputs, where n is an arbitrary positive integer, the parity bit is generated in n stages using only ##EQU1## 4-bit XOR cells. For 2.sup.2n+1 inputs, where n is an arbitrary positive integer, the parity bit is generated using ##EQU2## 4-bit XOR cells disposed in n rows and one 2-bit XOR cell disposed in the last row. The speed of operation of the XOR cells is further enhanced by using NMOS transistor logic within the XOR cells.

Abstract translation: 本发明公开了一种使用使用补码传输晶体管逻辑实现的4位XOR单元的快速奇偶校验位发生器。 对于22n个输入，其中n是任意正整数，奇偶校验位仅使用 4位XOR单元在n个阶段中生成。 对于22n + 1输入，其中n是任意的正整数，使用放置在最后一行中的n行和一个2位XOR单元中的 4位XOR单元产生奇偶校验位。 通过在XOR单元内使用NMOS晶体管逻辑来进一步增强XOR单元的工作速度。