公开(公告)号：US20240112953A1

公开(公告)日：2024-04-04

申请号：US18148231

申请日：2022-12-29

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West ,  Elizabeth Costner Stewart ,  Thomas Dyer Bonifield ,  Byron Lovell Williams ,  Kashyap Barot ,  Viresh Chinchansure ,  Sreeram N S

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76877 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/528

Abstract: A microelectronic device including a galvanic isolator with filler metal within an upper isolation element. The galvanic isolator includes a lower isolation element, an upper isolation element, and an inorganic dielectric plateau between the lower isolation element and the upper isolation element. The upper isolation element contains tines of filler metal which are electrically tied to each other and are electrically tied to the upper isolation element. The ends of the tines are rounded to minimize electric fields. The filler metal increases the overall metal density on the metal layer of the upper isolation element to meet the typical metal density requirements of modern microelectronic fabrication processing.

公开(公告)号：US11205695B2

公开(公告)日：2021-12-21

申请号：US15850999

申请日：2017-12-21

Applicant: Texas Instruments Incorporated

Inventor： Elizabeth C. Stewart ,  Jeffrey Alan West ,  Thomas D. Bonifield ,  Jay Sung Chun ,  Byron Lovell Williams

IPC: H01L21/02 ,  H01L23/522 ,  H01L49/02 ,  H01L21/027 ,  H01L21/311

Abstract: Methods of fabricating a thick oxide feature on a semiconductor wafer include forming a oxide layer having a thickness of at least six micrometers and depositing a photoresist layer on the oxide layer. The oxide layer has a first etch rate of X with a given etchant, the photoresist layer has a second etch rate of Y with the given etchant and the ratio of X:Y is less than 4:1. Prior to etching the photoresist layer and the oxide layer, the photoresist layer is patterned with a grayscale mask that creates a photoresist layer having a sidewall that forms an angle with the horizontal that is less than or equal to 10 degrees.

公开(公告)号：US10679935B2

公开(公告)日：2020-06-09

申请号：US16572346

申请日：2019-09-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jeffrey A. West ,  Byron Lovell Williams ,  David Leonard Larkin ,  Weidong Tian

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L49/02 ,  H01L21/768 ,  H01L23/00 ,  H01L21/02

Abstract: A method and structure suitable for, e.g., improving high voltage breakdown reliability of a microelectronic device such as a capacitor usable for galvanic isolation of two circuits. A first dielectric layer has a first dielectric constant located over a semiconductor substrate. A metal structure located over the first dielectric layer has a side surface. A second dielectric layer having a second different dielectric constant is located adjacent the metal structure. A dielectric structure located between the side surface of the metal structure and the second dielectric layer has the first dielectric constant.

公开(公告)号：US20200013713A1

公开(公告)日：2020-01-09

申请号：US16572346

申请日：2019-09-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jeffrey A. West ,  Byron Lovell Williams ,  David Leonard Larkin ,  Weidong Tian

IPC: H01L23/522 ,  H01L21/02 ,  H01L49/02 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

Abstract: A method and structure suitable for, e.g., improving high voltage breakdown reliability of a microelectronic device such as a capacitor usable for galvanic isolation of two circuits. A first dielectric layer has a first dielectric constant located over a semiconductor substrate. A metal structure located over the first dielectric layer has a side surface. A second dielectric layer having a second different dielectric constant is located adjacent the metal structure. A dielectric structure located between the side surface of the metal structure and the second dielectric layer has the first dielectric constant.

公开(公告)号：US20190198604A1

公开(公告)日：2019-06-27

申请号：US15850999

申请日：2017-12-21

Applicant: Texas Instruments Incorporated

Inventor： Elizabeth C. Stewart ,  Jeffrey Alan West ,  Thomas D. Bonifield ,  Jay Sung Chun ,  Byron Lovell Williams

IPC: H01L49/02 ,  H01L21/027 ,  H01L21/311 ,  H01L21/02 ,  H01L23/522

CPC classification number: H01L28/40 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/0274 ,  H01L21/31116 ,  H01L21/31144 ,  H01L23/5223

Abstract: Methods of fabricating a thick oxide feature on a semiconductor wafer include forming a oxide layer having a thickness of at least six micrometers and depositing a photoresist layer on the oxide layer. The oxide layer has a first etch rate of X with a given etchant, the photoresist layer has a second etch rate of Y with the given etchant and the ratio of X:Y is less than 4:1. Prior to etching the photoresist layer and the oxide layer, the photoresist layer is patterned with a grayscale mask that creates a photoresist layer having a sidewall that forms an angle with the horizontal that is less than or equal to 10 degrees.

公开(公告)号：US20180286802A1

公开(公告)日：2018-10-04

申请号：US15478615

申请日：2017-04-04

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey A. West ,  Byron Lovell Williams ,  David Leonard Larkin ,  Weidong Tian

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/02 ,  H01L49/02

CPC classification number: H01L23/5222 ,  H01L21/0217 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53295 ,  H01L28/40

Abstract: A method and structure for improving high voltage breakdown reliability of a microelectronic device, e.g., a galvanic digital isolator, involves providing an abatement structure around metal plate corners of a high voltage isolation capacitor to ameliorate the effects of an electric field formed thereat during operation of the device due to dielectric discontinuity.

公开(公告)号：US20180102216A1

公开(公告)日：2018-04-12

申请号：US15835666

申请日：2017-12-08

Applicant: Texas Instruments Incorporated

Inventor： Honglin Guo ,  Byron Lovell Williams

IPC: H01G2/08 ,  H01G4/018 ,  H01G4/18 ,  H01B3/30

CPC classification number: H01G2/08 ,  H01B3/306 ,  H01G4/018 ,  H01G4/18 ,  H01G4/33 ,  H01G4/40 ,  Y10T29/42

Abstract: A heated capacitor runs current through either a lower metal plate, an upper metal plate, a lower metal trace that lies adjacent to a lower metal plate, an upper metal trace that lies adjacent to an upper metal plate, or both a lower metal trace that lies adjacent to a lower metal plate and an upper metal trace that lies adjacent to an upper metal plate to generate heat from the resistance to remove moisture from a moisture-sensitive insulating layer.

公开(公告)号：US20150333055A1

公开(公告)日：2015-11-19

申请号：US14277851

申请日：2014-05-15

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West ,  Thomas D. Bonifield ,  Byron Lovell Williams

IPC: H01L27/06 ,  H01L21/02 ,  H01L21/8234 ,  H01L49/02 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L28/91 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/823481 ,  H01L27/0629 ,  H01L28/40 ,  H01L28/60 ,  H01L29/0692 ,  H01L29/66477 ,  H01L29/78 ,  H01L29/7833

Abstract: A microelectronic device contains a high voltage component having a high voltage node and a low voltage node. The high voltage node is isolated from the low voltage node by a main dielectric between the high voltage node and low voltage elements at a surface of the substrate of the microelectronic device. A lower-bandgap dielectric layer is disposed between the high voltage node and the main dielectric. The lower-bandgap dielectric layer contains at least one sub-layer with a bandgap energy less than a bandgap energy of the main dielectric. The lower-bandgap dielectric layer extends beyond the high voltage node continuously around the high voltage node. The lower-bandgap dielectric layer has an isolation break surrounding the high voltage node at a distance of at least twice the thickness of the lower-bandgap dielectric layer from the high voltage node.

Abstract translation: 微电子器件包含具有高电压节点和低电压节点的高电压分量。 高电压节点通过微电子器件的基板的表面处的高压节点和低电压元件之间的主电介质与低电压节点隔离。 低压隙电介质层设置在高电压节点和主电介质之间。 低带隙电介质层含有至少一个带隙能量小于主电介质带隙能量的子层。 低带隙电介质层围绕高压节点连续延伸超过高压节点。 较低带隙电介质层具有围绕高电压节点的隔离断裂，距离高压节点的至少两倍于低带隙电介质层的厚度。

公开(公告)号：US20240113094A1

公开(公告)日：2024-04-04

申请号：US17957847

申请日：2022-09-30

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey Alan West ,  Sreeram N. S. ,  Kashyap Barot ,  Thomas Dyer Bonifield ,  Byron Lovell Williams ,  Elizabeth Costner Stewart

IPC: H01L25/18 ,  H01F27/28 ,  H01F27/29 ,  H01F27/32 ,  H01L23/00 ,  H01L27/01

CPC classification number: H01L25/18 ,  H01F27/2804 ,  H01F27/29 ,  H01F27/323 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L27/01 ,  H01F2027/2809 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/06051 ,  H01L2224/06102 ,  H01L2224/06155 ,  H01L2224/0616 ,  H01L2224/4809 ,  H01L2224/48137 ,  H01L2224/48175 ,  H01L2224/4909

Abstract: A microelectronic device includes a galvanic isolation device on a silicon substrate and a semiconductor device on a semiconductor substrate. The galvanic isolation device includes a lower isolation element over the silicon substrate and an upper isolation element above the lower isolation element, separated by a dielectric plateau that comprises inorganic dielectric material extending from the lower isolation element to the upper isolation element. The galvanic isolation device includes lower bond pads connected to the lower isolation element adjacent to the dielectric plateau, and upper bond pads over the dielectric plateau, connected to the upper isolation element. The semiconductor device includes an active component, and device bond pads coupled to the active component. The microelectronic device includes first electrical connections to the lower bond pads and second electrical connections to the upper bond pads. The first electrical connections or the second electrical connections are connected to the device bond pads.

公开(公告)号：US11784212B2

公开(公告)日：2023-10-10

申请号：US17007726

申请日：2020-08-31

Applicant: Texas Instruments Incorporated

Inventor： Thomas Dyer Bonifield ,  Jeffrey Alan West ,  Byron Lovell Williams ,  Elizabeth Costner Stewart

IPC: H01L23/522 ,  H01L27/02 ,  H01L49/02

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L27/0292

Abstract: A galvanic isolation capacitor device includes a semiconductor substrate and a PMD layer over the semiconductor substrate. The PMD layer has a first thickness. A lower metal plate is over the PMD layer and an ILD layer is on the lower metal plate; the ILD layer has a second thickness. A ratio of the first thickness to the second thickness is between about 1 and 1.55 inclusive. A first upper metal plate over the ILD layer has a first area and a second upper metal plate over the ILD layer has a second area; a ratio of the first area to the second area is greater than about 5. The galvanic isolation capacitor device can be part of a multi-chip module.