公开(公告)号：US10418320B2

公开(公告)日：2019-09-17

申请号：US16127275

申请日：2018-09-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jeffrey A. West ,  Byron Lovell Williams ,  David Leonard Larkin ,  Weidong Tian

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L49/02 ,  H01L21/768 ,  H01L21/02

Abstract: A method and structure suitable for, e.g., improving high voltage breakdown reliability of a microelectronic device such as a capacitor usable for galvanic isolation of two circuits. A metal plate having a top surface and a side surface is located over a first dielectric layer. A second dielectric layer of a second different material is located over the first metal plate. A dielectric structure of the first material is located over the side surface of the metal plate and over the surface of the first dielectric layer.

公开(公告)号：US09818740B2

公开(公告)日：2017-11-14

申请号：US15368958

申请日：2016-12-05

Applicant: Texas Instruments Incorporated

Inventor： Weidong Tian ,  YuGuo Wang ,  Tathagata Chatterjee ,  Rajni J. Aggarwal

IPC: H01L27/06 ,  H01L29/739 ,  H01L29/06 ,  H01L29/10 ,  H01L29/45 ,  H01L29/417 ,  H01L21/8249 ,  H01L27/092

CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L27/092 ,  H01L29/0688 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/423 ,  H01L29/456 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7395

Abstract: An integrated circuit includes an NMOS transistor, a PMOS transistor and a vertical bipolar transistor. The vertical bipolar transistor has an intrinsic base with a band barrier at least 25 meV high at a surface boundary of the intrinsic base, except at an emitter-base junction with an emitter, and except at a base-collector junction with a collector. The intrinsic base may be laterally surrounded by an extrinsic base with a higher dopant density than the intrinsic base, wherein a higher dopant density provides the band barrier at lateral surfaces of the intrinsic base. A gate may be disposed on a gate dielectric layer over a top surface boundary of the intrinsic base adjacent to the emitter. The gate is configured to accumulate the intrinsic base immediately under the gate dielectric layer, providing the band barrier at the top surface boundary of the intrinsic base.

公开(公告)号：US20130256773A1

公开(公告)日：2013-10-03

申请号：US13899369

申请日：2013-05-21

Applicant: Texas Instruments Incorporated

Inventor： Shanjen Pan ,  Allan T. Mitchell ,  Weidong Tian

IPC: H01L27/07 ,  H01L23/525 ,  H01L21/82

CPC classification number: H01L27/0733 ,  H01L21/82 ,  H01L23/525 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In an embodiment of the invention, a method of fabricating a floating-gate PMOSFET (p-type metal-oxide semiconductor field-effect transistor) is disclosed. A silicide blocking layer (e.g. oxide, nitride) is used not only to block areas from being silicided but to also form an insulator on top of a poly-silicon gate. The insulator along with a top electrode (control gate) forms a capacitor on top of the poly-silicon gate. The poly-silicon gate also serves at the bottom electrode of the capacitor. The capacitor can then be used to capacitively couple charge to the poly-silicon gate. Because the poly-silicon gate is surrounded by insulating material, the charge coupled to the poly-silicon gate may be stored for a long period of time after a programming operation.

Abstract translation: 在本发明的实施例中，公开了制造浮栅PMOSFET（p型金属氧化物半导体场效应晶体管）的方法。 硅化物阻挡层（例如氧化物，氮化物）不仅用于阻挡不被硅化的区域，而且还在多晶硅栅极的顶部形成绝缘体。 绝缘体与顶部电极（控制栅极）一起形成在多晶硅栅极顶部的电容器。 多晶硅栅极还用于电容器的底部电极。 然后可以使用电容器将电荷电容耦合到多晶硅栅极。 由于多晶硅栅极被绝缘材料包围，所以耦合到多晶硅栅极的电荷可以在编程操作之后长时间存储。

公开(公告)号：US10679935B2

公开(公告)日：2020-06-09

申请号：US16572346

申请日：2019-09-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jeffrey A. West ,  Byron Lovell Williams ,  David Leonard Larkin ,  Weidong Tian

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L49/02 ,  H01L21/768 ,  H01L23/00 ,  H01L21/02

Abstract: A method and structure suitable for, e.g., improving high voltage breakdown reliability of a microelectronic device such as a capacitor usable for galvanic isolation of two circuits. A first dielectric layer has a first dielectric constant located over a semiconductor substrate. A metal structure located over the first dielectric layer has a side surface. A second dielectric layer having a second different dielectric constant is located adjacent the metal structure. A dielectric structure located between the side surface of the metal structure and the second dielectric layer has the first dielectric constant.

公开(公告)号：US20200013713A1

公开(公告)日：2020-01-09

申请号：US16572346

申请日：2019-09-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jeffrey A. West ,  Byron Lovell Williams ,  David Leonard Larkin ,  Weidong Tian

IPC: H01L23/522 ,  H01L21/02 ,  H01L49/02 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

Abstract: A method and structure suitable for, e.g., improving high voltage breakdown reliability of a microelectronic device such as a capacitor usable for galvanic isolation of two circuits. A first dielectric layer has a first dielectric constant located over a semiconductor substrate. A metal structure located over the first dielectric layer has a side surface. A second dielectric layer having a second different dielectric constant is located adjacent the metal structure. A dielectric structure located between the side surface of the metal structure and the second dielectric layer has the first dielectric constant.

公开(公告)号：US20180286802A1

公开(公告)日：2018-10-04

申请号：US15478615

申请日：2017-04-04

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey A. West ,  Byron Lovell Williams ,  David Leonard Larkin ,  Weidong Tian

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/02 ,  H01L49/02

CPC classification number: H01L23/5222 ,  H01L21/0217 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53295 ,  H01L28/40

Abstract: A method and structure for improving high voltage breakdown reliability of a microelectronic device, e.g., a galvanic digital isolator, involves providing an abatement structure around metal plate corners of a high voltage isolation capacitor to ameliorate the effects of an electric field formed thereat during operation of the device due to dielectric discontinuity.

公开(公告)号：US09548298B1

公开(公告)日：2017-01-17

申请号：US14942979

申请日：2015-11-16

Applicant: Texas Instruments Incorporated

Inventor： Weidong Tian ,  YuGuo Wang ,  Tathagata Chatterjee ,  Rajni J. Aggarwal

IPC: H01L21/338 ,  H01L27/06 ,  H01L29/732 ,  H01L21/8238 ,  H01L21/8222

CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L27/092 ,  H01L29/0688 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/423 ,  H01L29/456 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7395

Abstract: An integrated circuit includes an NMOS transistor, a PMOS transistor and a vertical bipolar transistor. The vertical bipolar transistor has an intrinsic base with a band barrier at least 25 meV high at a surface boundary of the intrinsic base, except at an emitter-base junction with an emitter, and except at a base-collector junction with a collector. The intrinsic base may be laterally surrounded by an extrinsic base with a higher dopant density than the intrinsic base, wherein a higher dopant density provides the band barrier at lateral surfaces of the intrinsic base. A gate may be disposed on a gate dielectric layer over a top surface boundary of the intrinsic base adjacent to the emitter. The gate is configured to accumulate the intrinsic base immediately under the gate dielectric layer, providing the band barrier at the top surface boundary of the intrinsic base.

Abstract translation: 集成电路包括NMOS晶体管，PMOS晶体管和垂直双极晶体管。 垂直双极晶体管具有在本征基极的表面边界处具有至少25meV高的带势垒的本征基极，除了在与发射极的发射极 - 基极结之外，并且除了在与集电极的基极 - 集电极结之外。 本征碱可以被具有比本征碱更高的掺杂剂密度的外在碱基侧向包围，其中较高的掺杂剂密度在本征碱的侧表面提供带阻挡。 栅极可以设置在与发射极相邻的本征基极的顶表面边界上的栅极电介质层上。 栅极被配置为在栅极电介质层的正下方积聚本征基极，从而在本征基极的顶部表面边界提供带状屏障。

公开(公告)号：US20160218062A1

公开(公告)日：2016-07-28

申请号：US14604660

申请日：2015-01-23

Applicant: Texas Instruments Incorporated

Inventor： Rajni J. Aggarwal ,  John P. Campbell ,  Kaiping Liu ,  Weidong Tian

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/31 ,  H01L49/02 ,  H01L21/768 ,  H01L21/02 ,  H01L21/285 ,  H01L21/321 ,  H01L23/528 ,  H01L23/29

CPC classification number: H01L23/5228 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/7684 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit with copper damascene interconnects includes a thin film resistor. Copper damascene metal lines are formed in a first ILD layer. A dielectric layer including an etch stop layer is formed on the first ILD layer and metal lines. Resistor heads of refractory metal are formed in the dielectric layer so that edges of the resistor heads are substantially coplanar with the adjacent dielectric layer. A thin film resistor layer is formed on the dielectric layer, extending onto the resistor heads. A second ILD layer is formed over the dielectric layer and the thin film resistor layer. Copper damascene vias are formed in the second ILD layer, making contact to the metal lines in the first ILD layer. Connections to the resistor heads are provided by the metal lines and/or the vias.

Abstract translation: 具有铜镶嵌互连的集成电路包括薄膜电阻器。 铜镶嵌金属线形成在第一ILD层中。 在第一ILD层和金属线上形成包括蚀刻停止层的电介质层。 难熔金属的电阻头形成在电介质层中，使得电阻头的边缘与相邻的电介质层基本上共面。 在电介质层上形成薄膜电阻层，延伸到电阻头上。 在电介质层和薄膜电阻层上形成第二ILD层。 在第二ILD层中形成铜大马士革通孔，与第一ILD层中的金属线接触。 与电阻头的连接由金属线和/或通孔提供。

公开(公告)号：US10211303B2

公开(公告)日：2019-02-19

申请号：US15223109

申请日：2016-07-29

Applicant: Texas Instruments Incorporated

Inventor： Ning Tan ,  Weidong Tian

IPC: H01L29/788 ,  H01L29/423 ,  H01L27/11521 ,  H01L21/266 ,  H01L21/28 ,  H01L21/8238 ,  H01L21/265 ,  H01L27/11524 ,  H01L27/11529 ,  H01L29/66 ,  H01L27/11539 ,  H01L27/11541 ,  H01L27/11543 ,  H01L23/528 ,  H01L23/532 ,  H01L27/11526 ,  H01L29/08 ,  H01L29/45 ,  H01L29/49 ,  H01L29/51 ,  H01L21/8234 ,  H01L27/105

Abstract: An integrated circuit contains a flash cell in which the top gate of the sense transistor is a metal sense gate over the floating gate. The source/drain regions of the sense transistor extend under the floating gate so that the source region is separated from the drain region by a sense channel length less than 200 nanometers. The floating gate is at least 400 nanometers wide, so the source/drain regions of the sense transistor extend under the floating gate at least 100 nanometers on each side. The integrated circuit is formed by forming the sense transistor source and drain regions before forming the floating gate.

公开(公告)号：US20190006276A1

公开(公告)日：2019-01-03

申请号：US16127275

申请日：2018-09-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jeffrey A. West ,  Byron Lovell Williams ,  David Leonard Larkin ,  Weidong Tian

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/02 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5222 ,  H01L21/0217 ,  H01L21/768 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53295 ,  H01L23/62 ,  H01L28/40 ,  H01L2224/05 ,  H01L2224/48463

Abstract: A method and structure suitable for, e.g., improving high voltage breakdown reliability of a microelectronic device such as a capacitor usable for galvanic isolation of two circuits. A metal plate having a top surface and a side surface is located over a first dielectric layer. A second dielectric layer of a second different material is located over the first metal plate. A dielectric structure of the first material is located over the side surface of the metal plate and over the surface of the first dielectric layer.