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公开(公告)号：US10483927B2
公开(公告)日：2019-11-19
申请号：US15856050
申请日：2017-12-27
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Aditya Sundar , Jasjot Singh Chadha
Abstract: In some examples, an amplifier comprises a first integrator to receive a differential input signal, a second integrator coupled to the first integrator, a third integrator coupled to the second integrator, and a comparator to receive outputs of the second and third integrators, to compare each of the outputs to a reference signal that is below a power supply rail voltage supplied to the amplifier, and to produce an error current based on the comparison. The amplifier also comprises a feedback connection between the comparator and inputs to the second integrator. The feedback connection injects the inputs to the second integrator with a current that is determined at least in part by the error current.
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公开(公告)号：US20180176683A1
公开(公告)日：2018-06-21
申请号：US15897177
申请日：2018-02-15
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Lars Risbo , Ryan Erik Lind , Jasjot Singh Chadha
CPC classification number: H04R3/02 , H03F3/185 , H03F3/2173 , H03F3/3022 , H03F3/45192 , H03F2200/03 , H03F2200/351 , H03F2200/411 , H04R3/00
Abstract: A system includes a class D amplifier and a current steering digital-to-analog converter (DAC) directly connected to the class D amplifier. The system also includes a common mode servo circuit coupled to a node interconnecting the current steering DAC to the class D amplifier. The common servo circuit amplifies a difference between a common mode signal determined from the node and a reference voltage and generates a feedback current to the node based on the amplified difference. A feed-forward common-mode compensation circuit is included to reduce an alternating current (AC) ripple from the class D amplifier. The feed-forward common-mode compensation circuit includes first and second resistors coupled to respective outputs of the class D amplifier. A current mirror is coupled to the first and second resistors and is configured to sink a current from the node to ground that approximates a common mode feedback current of the class D amplifier.
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公开(公告)号：US12003243B2
公开(公告)日：2024-06-04
申请号：US17232174
申请日：2021-04-16
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sumit Dubey , Jasjot Singh Chadha
Abstract: A circuit includes a filter, a comparator, and converter. A first input of the comparator couples to the output of the filter. A second input of the comparator is configured to receive ramp signal. An input of the converter couples to the output of the comparator. The circuit also includes a dual minimum pulse generator having an input coupled to the output of the converter. The dual minimum pulse generator is configured to, responsive to an input pulse on the input of the dual minimum pulse generator having a pulse width less than a predetermined delay time period, generate a pulse on the first output of the dual minimum pulse generator that has a pulse width equal to a sum of the pulse width of the input pulse and the predetermined delay time period. A driver is coupled to the output of the dual minimum pulse generator.
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公开(公告)号：US10158942B2
公开(公告)日：2018-12-18
申请号：US15897177
申请日：2018-02-15
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Lars Risbo , Ryan Erik Lind , Jasjot Singh Chadha
Abstract: A system includes a class D amplifier and a current steering digital-to-analog converter (DAC) directly connected to the class D amplifier. The system also includes a common mode servo circuit coupled to a node interconnecting the current steering DAC to the class D amplifier. The common servo circuit amplifies a difference between a common mode signal determined from the node and a reference voltage and generates a feedback current to the node based on the amplified difference. A feed-forward common-mode compensation circuit is included to reduce an alternating current (AC) ripple from the class D amplifier. The feed-forward common-mode compensation circuit includes first and second resistors coupled to respective outputs of the class D amplifier. A current mirror is coupled to the first and second resistors and is configured to sink a current from the node to ground that approximates a common mode feedback current of the class D amplifier.
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公开(公告)号：US20240223206A1
公开(公告)日：2024-07-04
申请号：US18147183
申请日：2022-12-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Venkata Ramanan Ramamurthy , Sumit Dubey , Jasjot Singh Chadha , Lokesh Kumar Botcha
Abstract: Examples of amplifiers and associated control blocks control analog and digital gains of such an amplifier to maintain a ripple voltage at the input/virtual terminals of an internal integrator below an upper limit. Such an example amplifier comprises digital and analog processing blocks. The digital processing block receives a digital audio signal and also includes a digital gain component. The analog processing block includes an analog gain component and an output stage having a supply voltage terminal. A boost controller receives the digital audio signal, and has a digital output and a boost voltage output to output a boost voltage. A digital controller receives the digital audio signal, and has a first digital input coupled to the digital output of the boost controller and a second digital input to receive a measurement value indicative of the outputted boost voltage. Based on its inputs, the digital controller controls the digital and analog gain components.
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Patent Agency Ranking
公开(公告)号：US10609477B1
公开(公告)日：2020-03-31
申请号：US16443897
申请日：2019-06-18
Applicant: Texas Instruments Incorporated
Inventor： Jasjot Singh Chadha , David Hernandez , Mukund Navada Kanyana , Rejin Kanjavalappil Raveendranath , Sahiti Priya C
Abstract: A boosted audio amplifier system includes a first digital interpolation filter configured to oversample an audio input signal at a first oversampling rate and includes a signal level detector having an input coupled to receive the oversampled audio input signal and configured to produce an audio input level signal. The system further includes a programmable delay buffer having inputs coupled to receive the oversampled audio input signal and a first delay signal. The programmable delay buffer adds a first delay to the oversampled audio input signal to produce a delayed input signal. The system also includes a first processor having inputs coupled to receive a battery voltage level signal, the audio input level signal and the first delay signal. The first processor is configured to produce boost control signals to regulate a boost voltage.
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公开(公告)号：US10397701B2
公开(公告)日：2019-08-27
申请号：US16175907
申请日：2018-10-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Lars Risbo , Ryan Erik Lind , Jasjot Singh Chadha
Abstract: A system includes a class D amplifier and a current steering digital-to-analog converter (DAC) directly connected to the class D amplifier. The system also includes a common mode servo circuit coupled to a node interconnecting the current steering DAC to the class D amplifier. The common servo circuit amplifies a difference between a common mode signal determined from the node and a reference voltage and generates a feedback current to the node based on the amplified difference. A feed-forward common-mode compensation circuit is included to reduce an alternating current (AC) ripple from the class D amplifier. The feed-forward common-mode compensation circuit includes first and second resistors coupled to respective outputs of the class D amplifier. A current mirror is coupled to the first and second resistors and is configured to sink a current from the node to ground that approximates a common mode feedback current of the class D amplifier.
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公开(公告)号：US20220094312A1
公开(公告)日：2022-03-24
申请号：US17503405
申请日：2021-10-18
Applicant: Texas Instruments Incorporated
Inventor： Shaik Asif Basha , Mohit Chawla , Jasjot Singh Chadha
Abstract: A pulse width modulated (PWM) amplifier includes a synchronization logic circuit having a first input configured to receive a bridge control signal and having a second input configured to receive a clock signal. The synchronization logic circuit is configured to provide a slope switch signal and a reference switch signal. The PWM amplifier includes a ramp generator having a first input configured to receive a first voltage supply and having a second input configured to receive a second voltage supply and having a third input configured to receive the reference switch signal and having a fourth input configured to receive the slope switch signal. The ramp generator is configured to provide a ramp signal having a first slope responsive to the slope switch signal in a first state and having a second slope responsive to the slope switch signal in a second state and to provide the clock signal.
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公开(公告)号：US11012058B2
公开(公告)日：2021-05-18
申请号：US16868104
申请日：2020-05-06
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sumit Dubey , Jasjot Singh Chadha
Abstract: A circuit includes a filter, a comparator, and converter. A first input of the comparator couples to the output of the filter. A second input of the comparator is configured to receive ramp signal. An input of the converter couples to the output of the comparator. The circuit also includes a dual minimum pulse generator having an input coupled to the output of the converter. The dual minimum pulse generator is configured to, responsive to an input pulse on the input of the dual minimum pulse generator having a pulse width less than a predetermined delay time period, generate a pulse on the first output of the dual minimum pulse generator that has a pulse width equal to a sum of the pulse width of the input pulse and the predetermined delay time period. A driver is coupled to the output of the dual minimum pulse generator.
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公开(公告)号：US10256779B2
公开(公告)日：2019-04-09
申请号：US15730410
申请日：2017-10-11
Applicant: TEXAS INSTRUMENTS INCORPORATED
Abstract: An amplifier includes a first transistor coupled to a first voltage source node and a second transistor coupled to a second voltage source node. The first and second transistors also couple together at an intermediate node. The amplifier further includes a third transistor coupled to the intermediate node and a fourth transistor coupled to the third transistor at a positive output node of the amplifier. Further, the amplifier includes a fifth transistor coupled to the intermediate node and a sixth transistor coupled to the fifth transistor at a negative output node of the amplifier.
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