公开(公告)号：US20250098266A1

公开(公告)日：2025-03-20

申请号：US18756202

申请日：2024-06-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Zhikai Tang ,  Jungwoo Joh ,  Ujwal Radhakrishna

IPC: H01L29/417 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

Abstract: Semiconductor devices with a source contact extending into a substrate are described. In one example, a semiconductor device comprises a semiconductor substrate including a source region, a gate region, a drain region, and a drain access region, where a heterojunction structure is disposed over the semiconductor substrate. The heterojunction structure includes a buffer layer over the semiconductor substrate and a barrier layer over the buffer layer. A gate stack is disposed over the barrier layer in the gate region. A source contact in the source region extends into the semiconductor substrate, including a first contact with a 2DEG in the heterojunction structure and a second contact with the semiconductor substrate.

公开(公告)号：US12046666B2

公开(公告)日：2024-07-23

申请号：US17330012

申请日：2021-05-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Chang Soo Suh ,  Sameer Prakash Pendharkar ,  Naveen Tipirneni ,  Jungwoo Joh

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/308 ,  H01L29/20 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/778 ,  H01L21/0254 ,  H01L21/308 ,  H01L29/2003 ,  H01L29/41725 ,  H01L29/42312 ,  H01L29/66462

Abstract: In some examples, a gallium nitride (GaN)-based transistor, comprises a substrate; a GaN layer supported by the substrate; an aluminum nitride gallium (AlGaN) layer supported by the GaN layer; a p-doped GaN structure supported by the AlGaN layer; and multiple p-doped GaN blocks supported by the AlGaN layer, each of the multiple p-doped GaN blocks physically separated from the remaining multiple p-doped GaN blocks, wherein first and second contours of a two-dimensional electron gas (2DEG) of the GaN-based transistor are at an interface of the AlGaN and GaN layers.

公开(公告)号：US11888027B2

公开(公告)日：2024-01-30

申请号：US17559635

申请日：2021-12-22

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Qhalid Fareed ,  Sridhar Seetharaman ,  Jungwoo Joh ,  Chang Soo Suh

IPC: H01L29/00 ,  H01L29/08 ,  H01L29/06 ,  H01L29/20

CPC classification number: H01L29/0847 ,  H01L29/0653 ,  H01L29/2003

Abstract: An electronic device includes an one of aluminum gallium nitride, aluminum nitride, indium aluminum nitride, or indium aluminum gallium nitride back barrier layer over a buffer structure, a gallium nitride layer over the back barrier layer, a hetero-epitaxy structure over the gallium nitride layer, first and second transistors over the hetero-epitaxy structure, and a hole injector having a doped gallium nitride structure over the hetero-epitaxy structure and a conductive structure partially over the doped gallium nitride structure to inject holes to form a hole layer proximate an interface of the back barrier layer and the buffer structure to mitigate vertical electric field back gating effects for the first transistor.

公开(公告)号：US20220231156A1

公开(公告)日：2022-07-21

申请号：US17499462

申请日：2021-10-12

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Jungwoo Joh

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/66

Abstract: A microelectronic device includes a GaN FET on a substrate such as silicon and a buffer layer of III-N semiconductor material. The GaN FET includes both source contacts and drain contacts to a channel layer of III-N semiconductor material. Source contacts to the source region are placed farther from the gate electrode fingertip than drain contacts to the drain region.

公开(公告)号：US11177378B2

公开(公告)日：2021-11-16

申请号：US16895111

申请日：2020-06-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jungwoo Joh ,  Naveen Tipirneni ,  Chang Soo Suh ,  Sameer Pendharkar

IPC: H01L29/778 ,  H01L21/265 ,  H01L21/266 ,  H01L21/308 ,  H01L29/06 ,  H01L29/08 ,  H01L29/20 ,  H01L29/417 ,  H01L29/66

Abstract: A High Electron Mobility Transistor (HEMT) includes an active layer on a substrate, and a Group IIIA-N barrier layer on the active layer. An isolation region is through the barrier layer to provide at least one isolated active area including the barrier layer on the active layer. A gate is over the barrier layer. A drain includes at least one drain finger including a fingertip having a drain contact extending into the barrier layer to contact to the active layer and a source having a source contact extending into the barrier layer to contact to the active layer. The source forms a loop that encircles the drain. The isolation region includes a portion positioned between the source and drain contact so that there is a conduction barrier in a length direction between the drain contact of the fingertip and the source.

公开(公告)号：US20210257312A1

公开(公告)日：2021-08-19

申请号：US17176995

申请日：2021-02-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jungwoo Joh ,  Young-Soon Park

IPC: H01L23/552 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/48 ,  H01L29/78 ,  H05K1/02

Abstract: A semiconductor device a strapped interconnect line, which in turn includes a first interconnect line at a first level above a semiconductor substrate, and a second interconnect line at a second level above the interconnect substrate. A dielectric capping layer is located directly on the first interconnect line. A plurality of strapping vias are connected between the first interconnect line and the second interconnect line. Each of the strapping vias extends from a first side of the first interconnect line to a second side of the second interconnect line.

公开(公告)号：US11067620B2

公开(公告)日：2021-07-20

申请号：US16400336

申请日：2019-05-01

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Jungwoo Joh ,  Pinghai Hao ,  Sameer Pendharkar

IPC: G01R31/26 ,  G01R27/26

Abstract: A method includes applying a DC stress condition to a transistor for a predetermined stress time, measuring an impedance of the transistor after the predetermined stress time, and repeating the application of the DC stress condition and the measurement of the impedance until the measured impedance exceeds an impedance threshold or a total stress time exceeds a time threshold, where the DC stress condition includes applying a non-zero drain voltage signal to a drain terminal of the transistor, applying a gate voltage signal to a gate terminal of the transistor, and applying a non-zero source current signal to a source terminal of the transistor.

公开(公告)号：US10964803B2

公开(公告)日：2021-03-30

申请号：US16194794

申请日：2018-11-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dong Seup Lee ,  Jungwoo Joh ,  Pinghai Hao ,  Sameer Pendharkar

IPC: H01L29/778 ,  H01L29/08 ,  H01L29/66 ,  H01L29/20 ,  H01L29/06 ,  H01L29/10 ,  H01L21/265 ,  H01L29/417 ,  H01L29/423

Abstract: In some examples, a transistor comprises a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the GaN layer; and a first doped region positioned in a drain access region and extending from the top side into the GaN layer.

公开(公告)号：US20180190550A1

公开(公告)日：2018-07-05

申请号：US15439191

申请日：2017-02-22

Applicant: Texas Instruments Incorporated

Inventor： Dong Seup Lee ,  Jungwoo Joh ,  Sameer Pendharkar

IPC: H01L21/66 ,  H01L29/06 ,  H01L23/544 ,  H01L29/40 ,  H01L29/20 ,  H01L29/417 ,  H01L27/088 ,  G01R31/12 ,  G01R31/28

CPC classification number: H01L22/34 ,  G01R31/12 ,  G01R31/2884 ,  H01L23/544 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/41725

Abstract: A first set of test structures for a gallium nitride (GaN) transistor that includes N field plates is disclosed, where N is an integer and X is an integer between 0 and N inclusive. A test structure TSX of the first set of test structures includes a GaN substrate, a dielectric material overlying the GaN substrate, a respective source contact abutting the GaN substrate and a respective drain contact abutting the GaN substrate. The test structure TSX also includes a respective gate overlying the substrate and lying between the respective source contact and the respective drain contact and X respective field plates corresponding to X of the N field plates of the GaN transistor, the X respective field plates including field plates that are nearest to the GaN substrate.

公开(公告)号：US20240429233A1

公开(公告)日：2024-12-26

申请号：US18828356

申请日：2024-09-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen Tipirneni ,  Maik Peter Kaufmann ,  Michael Lueders ,  Jungwoo Joh

IPC: H01L27/06 ,  H01L21/8252 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778 ,  H02M3/156 ,  H03K3/037

Abstract: The present invention provides a capacitor having a first structure made of a metal layer and a second structure made of the same metal layer and a dielectric layer between the first and the second metal structure, wherein the dielectric layer has a relative permittivity greater than 4, in particular greater than 6. It also provides a monolithically integrated circuit including such a capacitor and optionally other components. A method of manufacturing such a capacitor is also provided.