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公开(公告)号：US10566991B2
公开(公告)日：2020-02-18
申请号：US16373614
申请日：2019-04-02
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Peng Cao , Amit Kumar Gupta
Abstract: A delta-sigma modulator architecture with idle tone suppression based on injecting an out-of-band signal includes: modulator input circuitry to provide a modulator input signal; modulator loop circuitry to quantize the modulator input signal to generate a modulator output signal at an oversampling frequency, and to provide a feedback signal. Digital filtering circuitry filters the modulator output signal to provide a digital output signal at a data rate frequency related to the oversampling frequency by a defined oversampling ratio. Out-of-band (OoB) signal generator circuitry injects a deterministic OoB injection signal at a defined OoB frequency outside of a target frequency band. The modulator input circuitry combines the analog input signal, the feedback signal, and the OoB injection signal into the modulator input signal. The digital filtering circuitry filters the OoB injection signal. The OoB injection signal can be selectively defined to suppress idle tones generated in the modulator loop circuitry.
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公开(公告)号：US09762259B1
公开(公告)日：2017-09-12
申请号：US15401957
申请日：2017-01-09
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Xiao Pu , Krishnaswamy Nagaraj , Peng Cao
Abstract: A notch filter in a sigma-delta modulator loop filter increases SNR by limiting in-band quantization noise around a frequency to which the notch filter is precisely tuned. A tuning mode controller isolates the notch filter from other loop filter stages. A bias voltage is applied to the notch filter, causing it to resonate. Tuning mode switches insert the notch filter into a frequency-locked loop (“FLL”) circuit as a variable frequency oscillator component of the FLL. An ADC operational mode input signal is applied to the FLL as a reference signal. A tuning control component of the FLL adjusts a tunable feedback element in the notch filter to drive the FLL error signal to zero in order to precisely tune the notch filter to the center frequency of the ADC input signal. Tuning inputs to the tunable feedback element are then latched prior to re-inserting the notch filter into the modulator.
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公开(公告)号：US20240405778A1
公开(公告)日：2024-12-05
申请号：US18326245
申请日：2023-05-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Vishnu Ravinuthula , Peng Cao , Chienyu Huang
IPC: H03L7/099
Abstract: An integrated circuit (IC) includes an oscillator circuit having a control input. A control circuit has a control output coupled to the control input. The control circuit is configured to generate a control signal to the control input of the oscillator circuit to cause: the oscillator circuit to be configured as a frequency-locked loop in response to the control signal being in a first state; and the oscillator circuit to be configured as a phase-locked loop in response to the control signal being in a second state.
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4.发明公开公开(公告)号：US20240146267A1
公开(公告)日：2024-05-02
申请号：US18187870
申请日：2023-03-22
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Chienyu Huang , Peng Cao , Kevin Scoones
IPC: H03F3/45
CPC classification number: H03F3/45475 , H03F2200/375
Abstract: The techniques and circuits, described herein, include solutions for auto-zeroing in auto-zero amplifiers in the presence of high frequency alternating current (AC) noise. In some aspects, first and second inputs of an auto-zero amplifier are coupled to a differential voltage with high AC noise. During an auto-zero phase, a first switching network decouples the inputs of a first amplifier, comprised within the auto-zero amplifier, from the differential voltage with high AC noise. In some examples, the inputs of the first amplifier may be connected to a regulated direct current (DC) voltage. The regulated DC voltage provides a more accurate auto-zero for the auto-zero amplifier, such that higher overall accuracy is achieved during an operation phase.
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公开(公告)号：US11543845B2
公开(公告)日：2023-01-03
申请号：US16908784
申请日：2020-06-23
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Maciej Piotr Jankowski , Peng Cao
Abstract: A method comprising activating an internal switch within a packaged electronic device to connect to a reference ground of an internal voltage source to a first input of an analog front end, receiving an external ground potential voltage at a first package pin of the packaged electronic device, generating a zero detector output signal for the packaged electronic device at a second package pin, activating the internal switch to connect the first input of the analog front end to the internal voltage source, receiving a second voltage level at the first package pin that generates a second output signal that matches the zero detector output signal, and receiving trim instructions to trim an internal voltage generated by the internal voltage source to a voltage level that is closer to a target voltage level.
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Patent Agency Ranking
公开(公告)号：US20190305794A1
公开(公告)日：2019-10-03
申请号：US16373614
申请日：2019-04-02
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Peng Cao , Amit Kumar Gupta
IPC: H03M3/00
Abstract: A delta-sigma modulator architecture with idle tone suppression based on injecting an out-of-band signal includes: modulator input circuitry to provide a modulator input signal; modulator loop circuitry to quantize the modulator input signal to generate a modulator output signal at an oversampling frequency, and to provide a feedback signal. Digital filtering circuitry filters the modulator output signal to provide a digital output signal at a data rate frequency related to the oversampling frequency by a defined oversampling ratio. Out-of-band (OoB) signal generator circuitry injects a deterministic OoB injection signal at a defined OoB frequency outside of a target frequency band. The modulator input circuitry combines the analog input signal, the feedback signal, and the OoB injection signal into the modulator input signal. The digital filtering circuitry filters the OoB injection signal. The OoB injection signal can be selectively defined to suppress idle tones generated in the modulator loop circuitry.
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公开(公告)号：US10284222B1
公开(公告)日：2019-05-07
申请号：US16121906
申请日：2018-09-05
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Amit Kumar Gupta , Peng Cao
IPC: H03M3/00
Abstract: An analog-to-digital converter (ADC) device includes a delta-sigma modulator having at least one integrator and a quantizer configured to receive an output of the at least one integrator. The delta-sigma modulator also includes digital-to-analog converter (DAC) capacitor bank, a sampling capacitor bank, and a pre-charge capacitor bank, each selectively coupled to an input node of the at least one integrator. The delta-sigma modulator also includes a pre-charge signal generator coupled to the pre-charge capacitor bank. The pre-charge signal generator is configured to generate a pre-charge signal to charge the pre-charge capacitor bank based at least in part on an output code of the quantizer.
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公开(公告)号：US09729165B2
公开(公告)日：2017-08-08
申请号：US15153384
申请日：2016-05-12
Applicant: Texas Instruments Incorporated
Inventor： Amit K. Gupta , Peng Cao , Venkatesh Acharya
Abstract: A delta-sigma Analog-to-Digital Converter (ADC) (IC) which includes an input feed-forward path extending from an input to the ADC to a feed-forward summing circuit disposed between a loop filter and quantizer of the ADC, and a filter disposed in the feed-forward path as an apparatus for improving distortion performance in the delta-sigma ADC. The filter may be a low pass filter, for example, a Resistor-Capacitor (RC) circuit. The filter may have a cut-off frequency outside the ADC's passband. The filtering provided may be continuous-time filtering, even if the delta-sigma ADC is a discrete-time delta-sigma ADC.
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公开(公告)号：US20170194983A1
公开(公告)日：2017-07-06
申请号：US15463780
申请日：2017-03-20
Applicant: Texas Instruments Incorporated
Inventor： Peng Cao , Amit Kumar Gupta , Venkata Krishnan Kidambi Srinivasan
IPC: H03M3/00
Abstract: A dual delta-sigma modulator includes a first modulator, a second modulator, and a shared amplifier coupled to the first and second modulators. The first modulator includes an integrator configured to generate a first modulator output signal. The second modulator includes a second integrator configured to generate a second modulator output signal. The shared amplifier is configured to assist the first integrator integrating a difference between a first analog input signal and a first modulator output signal from the first modulator during a first period of time and to assist the second integrator integrate a difference between a second analog input signal and a second modulator output signal from the second modulator during a second period of time.
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10.发明申请Delta-Sigma Analog-to-Digital Converter Topology with Improved Distortion Performance 有权Delta-Sigma模数转换器拓扑，具有改进的失真性能公开(公告)号：US20160336956A1
公开(公告)日：2016-11-17
申请号：US15153384
申请日：2016-05-12
Applicant: Texas Instruments Incorporated
Inventor： Amit K. Gupta , Peng Cao , Venkatesh Acharya
IPC: H03M3/00
Abstract: A delta-sigma Analog-to-Digital Converter (ADC) (IC) which includes an input feed-forward path extending from an input to the ADC to a feed-forward summing circuit disposed between a loop filter and quantizer of the ADC, and a filter disposed in the feed-forward path as an apparatus for improving distortion performance in the delta-sigma ADC. The filter may be a low pass filter, for example, a Resistor-Capacitor (RC) circuit. The filter may have a cut-off frequency outside the ADC's passband. The filtering provided may be continuous-time filtering, even if the delta-sigma ADC is a discrete-time delta-sigma ADC.
Abstract translation: 一种Δ-Σ模数转换器（ADC），其包括从输入到ADC延伸到设置在ADC的环路滤波器和量化器之间的前馈求和电路的输入前馈路径，以及 布置在前馈路径中的滤波器作为用于改进Δ-ΣADC中的失真性能的装置。 滤波器可以是低通滤波器，例如电阻 - 电容（RC）电路。 滤波器可能在ADC通带外部具有截止频率。 所提供的滤波可以是连续时间滤波，即使Δ-ΣADC是离散时间Δ-ΣADC。
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