公开(公告)号：US11290118B2

公开(公告)日：2022-03-29

申请号：US17128791

申请日：2020-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Srinivas Theertham ,  Jagdish Chand ,  Yogesh Darwhekar ,  Subhashish Mukherjee ,  Jayawardan Janardhanan ,  Uday Kiran Meda ,  Arpan Sureshbhai Thakkar ,  Apoorva Bhatia ,  Pranav Kumar

IPC: H03L7/23 ,  H03M1/66 ,  H03L7/085 ,  H03L7/099

Abstract: A frequency synthesizer includes a phase-locked loop (PLL). The PLL includes a first voltage-controlled oscillator (VCO) and a second VCO, each comprising an oscillator, a capacitor bank, and a bias circuit. The capacitor bank is configured to selectably adjust an output frequency of the oscillator. The bias circuit is configured to provide a bias current to the oscillator, and includes a current digital-to-analog converter (IDAC), and an amplifier coupled to the IDAC and configured to drive the oscillator.

公开(公告)号：US10658357B2

公开(公告)日：2020-05-19

申请号：US15990880

申请日：2018-05-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Pranav Kumar ,  Yogesh Darwhekar

IPC: H01L27/06 ,  H03K19/018 ,  H01L29/73

Abstract: A circuit includes a first bipolar junction transistor (BJT) including a first base, a first collector, and a first emitter, the first collector connected to a first supply voltage node and a second BJT including a second base, a second collector, and a second emitter, the second collector connected to the first emitter at an output node. The circuit also includes a capacitor including a first capacitor terminal and a second capacitor terminal, the first capacitor terminal connected to the second emitter of the second BJT and the second capacitor terminal connected to a second supply voltage node. A current source device is also included that is connected in parallel with the capacitor.

公开(公告)号：US11977407B2

公开(公告)日：2024-05-07

申请号：US17683185

申请日：2022-02-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Apoorva Bhatia ,  Pranav Kumar ,  Abhrarup Barman Roy ,  Peeyoosh Mirajkar ,  Raghavendra Reddy

IPC: G06F1/12 ,  G06F1/08 ,  H03K3/037 ,  H03K19/20

CPC classification number: G06F1/12 ,  G06F1/08 ,  H03K3/037 ,  H03K19/20

Abstract: In an example, a system is adapted to be coupled to a load device having a load clock. The system includes a clock generation device with a pin. The system also includes a capture circuit coupled to the pin and operable to sample a value at the pin. The system includes a D flip-flop having a data input coupled to the capture circuit, a clock input coupled to a clock, and having an output, where the D flip-flop is operable to provide, at the output, a system reference event (SYSREF) signal to align the load clock to the clock, based at least in part on the value at the pin.

公开(公告)号：US11387834B1

公开(公告)日：2022-07-12

申请号：US17319819

申请日：2021-05-13

Applicant: Texas Instruments Incorporated

Inventor： Pranav Kumar ,  Abhrarup Barman Roy ,  Apoorva Bhatia ,  Arpan Sureshbhai Thakkar ,  Jagdish Chand

IPC: H03L7/091 ,  H03L7/18 ,  H03L7/081 ,  H03L7/099 ,  H03L7/089

Abstract: An example apparatus includes: a first flip flop having a first output and a first reset input, a second flip flop having a first data input, a second output, and a second reset input, the second reset input coupled to the first reset input, a logic gate having a first logic input, a second logic input, and a first logic output, the first logic input coupled to the first output and the second logic input coupled to the second output, a delay cell having a delay cell input and a delay cell output, the delay cell input coupled to the first logic output and the delay cell output coupled to the first reset input and the second reset input, and pulse swallowing circuitry having a circuitry input and a circuitry output, the circuitry input coupled to the second output and the circuitry output coupled to the first data input.

公开(公告)号：US10608853B1

公开(公告)日：2020-03-31

申请号：US16130087

申请日：2018-09-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yogesh Darwhekar ,  Pranav Kumar ,  Arpan Thakkar ,  Naveen Mahadev ,  Srikanth Manian

IPC: H04L27/00 ,  H04L27/38 ,  H04L27/152 ,  H04L27/148

Abstract: A receiver circuit includes a quadrature signal generator to generate an in-phase (I) signal and a quadrature (Q) signal from a local oscillator signal and an IQ phase sense and control circuit to generate a phase adjustment code responsive to a phase error between quadrature signals generated by a plurality of mixers. The receiver circuit also includes a phase corrector to adjust a phase difference between the I and Q signals from the quadrature signal generator to generate corrected I and Q signals to be provided to the plurality of mixers.

公开(公告)号：US20230061672A1

公开(公告)日：2023-03-02

申请号：US17462941

申请日：2021-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Arpan Sureshbhai Thakkar ,  Pranav Kumar ,  Yogesh Darwhekar

IPC: H03H11/04 ,  H03K5/1252 ,  G06F1/08

Abstract: A circuit for subharmonic detection includes in-phase and quadrature mixers, first and second filters, and a processing circuit. The in-phase mixer has a first mixer input and a first mixer output. The quadrature mixer has a second mixer input and a second mixer output, the first mixer input coupled to the second mixer input. The first filter circuit has a first filter input and a first filter output, the first filter input coupled to the first mixer output. The second filter circuit has a second filter input and a second filter output, the second filter input coupled to the second mixer output. The processing circuit has a first input and a second input, the first input of the processing circuit coupled to the first filter output, the second input of the processing circuit coupled to the second filter output. The processing circuit is configured to detect a subharmonic component of a wave at the first mixer input and the second mixer input using a first direct current (DC) component at the first input of the processing circuit and a second DC component at the second input of the processing circuit.

公开(公告)号：US10924309B2

公开(公告)日：2021-02-16

申请号：US16793486

申请日：2020-02-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yogesh Darwhekar ,  Pranav Kumar ,  Arpan Thakkar ,  Naveen Mahadev ,  Srikanth Manian

IPC: H04L27/00 ,  H04L27/38 ,  H04L27/152 ,  H04L27/148

Abstract: A receiver circuit includes a quadrature signal generator to generate an in-phase (I) signal and a quadrature (Q) signal from a local oscillator signal and an IQ phase sense and control circuit to generate a phase adjustment code responsive to a phase error between quadrature signals generated by a plurality of mixers. The receiver circuit also includes a phase corrector to adjust a phase difference between the I and Q signals from the quadrature signal generator to generate corrected I and Q signals to be provided to the plurality of mixers.

公开(公告)号：US11626840B2

公开(公告)日：2023-04-11

申请号：US17462941

申请日：2021-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Arpan Sureshbhai Thakkar ,  Pranav Kumar ,  Yogesh Darwhekar

IPC: H03D7/14 ,  H03K5/1252

Abstract: A circuit for subharmonic detection includes in-phase and quadrature mixers, first and second filters, and a processing circuit. The in-phase mixer has a first mixer input and a first mixer output. The quadrature mixer has a second mixer input and a second mixer output, the first mixer input coupled to the second mixer input. The first filter circuit has a first filter input and a first filter output, the first filter input coupled to the first mixer output. The second filter circuit has a second filter input and a second filter output, the second filter input coupled to the second mixer output. The processing circuit has a first input and a second input, the first input of the processing circuit coupled to the first filter output, the second input of the processing circuit coupled to the second filter output. The processing circuit is configured to detect a subharmonic component of a wave at the first mixer input and the second mixer input using a first direct current (DC) component at the first input of the processing circuit and a second DC component at the second input of the processing circuit.