公开(公告)号：US20240296065A1

公开(公告)日：2024-09-05

申请号：US18661804

申请日：2024-05-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy Anderson ,  Joseph Zbiciak

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38 ,  G06F15/76

CPC classification number: G06F9/485 ,  G06F9/30014 ,  G06F9/30047 ,  G06F9/30145 ,  G06F9/345 ,  G06F9/383 ,  G06F15/76

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream recalled memory. Streams are started by one of two types of stream start instructions. A stream start ordinary instruction specifies a register storing a stream start address and a register of storing a stream definition template which specifies stream parameters. A stream start short-cut instruction specifies a register storing a stream start address and an implied stream definition template. A functional unit is responsive to a stream operand instruction to receive at least one operand from a stream head register. The stream template supports plural nested loops with short-cut start instructions limited to a single loop. The stream template supports data element promotion to larger data element size with sign extension or zero extension. A set of allowed stream short-cut start instructions includes various data sizes and promotion factors.

公开(公告)号：US20220261373A1

公开(公告)日：2022-08-18

申请号：US17735255

申请日：2022-05-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： David M. Thompson ,  Timothy Anderson ,  Joseph Zbiciak ,  Abhijeet A. Chachad ,  Kai Chirca ,  Matthew D. Pierson

IPC: G06F13/42 ,  G06F13/362

Abstract: The Multicore Bus Architecture (MBA) protocol includes a novel technique of sharing the same physical channel for all transaction types. Two channels, the Transaction Attribute Channel (TAC) and the Transaction Data Channel (TDC) are used. The attribute channel transmits bus transaction attribute information optionally including a transaction type signal, a transaction ID, a valid signal, a bus agent ID signal, an address signal, a transaction size signal, a credit spend signal and a credit return signal. The data channel connected a data subset of the signal lines of the bus separate from the attribute subset of signal lines the bus. The data channel optionally transmits a data valid signal, a transaction ID signal, a bus agent ID signal and a last data signal to mark the last data of a current bus transaction.

公开(公告)号：US20220261245A1

公开(公告)日：2022-08-18

申请号：US17738993

申请日：2022-05-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy Anderson ,  Duc Quang Bui ,  Joseph Zbiciak

IPC: G06F9/30 ,  G06F9/38

Abstract: A technique for method for executing instructions in a processor includes receiving a first instruction, receiving a second instruction, identifying a functional unit specified by an opcode contained in an opcode field of the first instruction, selecting a field of the second instruction that contains predicate information based on the identified functional unit, and executing the first instruction in a conditional manner using the identified functional unit and the predicate information contained in the selected field of the second instruction.

公开(公告)号：US11321268B2

公开(公告)日：2022-05-03

申请号：US14530266

申请日：2014-10-31

Applicant: Texas Instruments Incorporated

Inventor： David M. Thompson ,  Timothy Anderson ,  Joseph Zbiciak ,  Abhijeet A. Chachad ,  Kai Chirca ,  Matthew D. Pierson

IPC: G06F13/362 ,  G06F13/42

Abstract: The Multicore Bus Architecture (MBA) protocol includes a novel technique of sharing the same physical channel for all transaction types. Two channels, the Transaction Attribute Channel (TAC) and the Transaction Data Channel (TDC) are used. The attribute channel transmits bus transaction attribute information optionally including a transaction type signal, a transaction ID, a valid signal, a bus agent ID signal, an address signal, a transaction size signal, a credit spend signal and a credit return signal. The data channel connected a data subset of the signal lines of the bus separate from the attribute subset of signal lines the bus. The data channel optionally transmits a data valid signal, a transaction ID signal, a bus agent ID signal and a last data signal to mark the last data of a current bus transaction.

公开(公告)号：US20210406021A1

公开(公告)日：2021-12-30

申请号：US17472852

申请日：2021-09-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Timothy Anderson

IPC: G06F9/32 ,  G06F9/38 ,  G06F9/30 ,  G06F13/16 ,  G06F13/40 ,  G06F12/0875 ,  G06F12/0897 ,  G06F9/345 ,  G06F11/00 ,  G06F12/02

Abstract: A streaming engine employed in a digital data processor specifies fixed first and second read only data streams. Corresponding stream address generator produces address of data elements of the two streams. Corresponding steam head registers stores data elements next to be supplied to functional units for use as operands. The two streams share two memory ports. A toggling preference of stream to port ensures fair allocation. The arbiters permit one stream to borrow the other's interface when the other interface is idle. Thus one stream may issue two memory requests, one from each memory port, if the other stream is idle. This spreads the bandwidth demand for each stream across both interfaces, ensuring neither interface becomes a bottleneck.

公开(公告)号：US20210390018A1

公开(公告)日：2021-12-16

申请号：US17408561

申请日：2021-08-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Timothy Anderson

IPC: G06F11/10 ,  G06F11/14 ,  G06F9/345 ,  G06F12/0817 ,  G06F12/0875 ,  G06F12/0897 ,  G06F9/30 ,  G06F9/38 ,  G06F11/00

Abstract: Disclosed embodiments relate to a streaming engine employed in, for example, a digital signal processor. A fixed data stream sequence including plural nested loops is specified by a control register. The streaming engine includes an address generator producing addresses of data elements and a steam head register storing data elements next to be supplied as operands. The streaming engine fetches stream data ahead of use by the central processing unit core in a stream buffer. Parity bits are formed upon storage of data in the stream buffer which are stored with the corresponding data. Upon transfer to the stream head register a second parity is calculated and compared with the stored parity. The streaming engine signals a parity fault if the parities do not match. The streaming engine preferably restarts fetching the data stream at the data element generating a parity fault.

公开(公告)号：US10560428B2

公开(公告)日：2020-02-11

申请号：US15679307

申请日：2017-08-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Amritpal Singh Mundra ,  Brian J. Karguth ,  Timothy Anderson ,  Kai Chirca ,  Charles Fuoco

IPC: H04L29/06

Abstract: A flexible hybrid firewall architecture that allows a mix of firewalls at end points in front of a target and at the initiator points. Groups of Priv-IDs may be created where each group is isolated from other worlds, with all firewalls controlled by a device management and security module.

公开(公告)号：US20190121697A1

公开(公告)日：2019-04-25

申请号：US16133434

申请日：2018-09-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joseph Zbiciak ,  Timothy Anderson

IPC: G06F11/10 ,  G06F12/0897 ,  G06F9/30 ,  G06F9/38 ,  G06F9/345 ,  G06F11/00 ,  G06F12/0817 ,  G06F12/0875 ,  G06F11/14

Abstract: Disclosed embodiments relate to a streaming engine employed in, for example, a digital signal processor. A fixed data stream sequence including plural nested loops is specified by a control register. The streaming engine includes an address generator producing addresses of data elements and a steam head register storing data elements next to be supplied as operands. The streaming engine fetches stream data ahead of use by the central processing unit core in a stream buffer. Parity bits are formed upon storage of data in the stream buffer which are stored with the corresponding data. Upon transfer to the stream head register a second parity is calculated and compared with the stored parity. The streaming engine signals a parity fault if the parities do not match. The streaming engine preferably restarts fetching the data stream at the data element generating a parity fault.

公开(公告)号：US20160188408A1

公开(公告)日：2016-06-30

申请号：US14587234

申请日：2014-12-31

Applicant: Texas Instruments Incorporated

Inventor： Timothy Anderson ,  Joseph Zbiciak ,  Abhijeet A. Chachad ,  Kai Chirca ,  Naveen Bhoria ,  David M. Thompson ,  Jonathan (Son) Hung Tran

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F3/0673 ,  G06F3/0619 ,  G06F3/064 ,  G06F11/1048

Abstract: This invention is data processing apparatus and method. Data is protecting from corruption using an error correction code by generating an error correction code corresponding to the data. In this invention the data and the corresponding error correction code are carried forward to another set of registers without regenerating the error correction code or using the error correction code for error detection or correction. Only later are error correction detection and correction actions taken. The differing data/error correction code registers may be in differing pipeline phases in the data processing apparatus. This invention forwards the error correction code with the data through the entire datapath that carries the data. This invention provides error protection to the whole datapath without requiring extensive hardware or additional time.

Abstract translation: 本发明是数据处理装置和方法。 通过产生对应于该数据的纠错码，使用纠错码来防止数据损坏。 在本发明中，将数据和相应的纠错码转发到另一组寄存器，而不用再生纠错码或使用纠错码进行错误检测或校正。 只有以后才采取纠错检测和纠正措施。 在数据处理装置中不同的数据/纠错码寄存器可能处于不同的流水线相位。 本发明通过携带数据的整个数据路径转发具有数据的纠错码。 本发明为整个数据路径提供错误保护，而不需要大量硬件或额外的时间。

公开(公告)号：US20150019835A1

公开(公告)日：2015-01-15

申请号：US14327038

申请日：2014-07-09

Applicant: Texas Instruments Incorporated

Inventor： Timothy Anderson ,  Duc Quang Bui ,  Joseph Zbiciak

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30072 ,  G06F9/30101 ,  G06F9/30145 ,  G06F9/30185 ,  G06F9/3853 ,  G06F9/3867 ,  G06F9/3885

Abstract: A predication method for vector processors that minimizes the use of embedded predicate fields in most instructions by using separate condition code extensions. Dedicated predicate registers provide fine grain predication of vector instructions where each bit of a predicate register controls 8 bit of the vector data.

Abstract translation: 矢量处理器的预测方法，通过使用单独的条件代码扩展来最大限度地减少大多数指令中嵌入谓词字段的使用。 专用谓词寄存器提供向量指令的精细粒度预测，其中谓词寄存器的每个位控制向量数据的8位。