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公开(公告)号：US10131539B2
公开(公告)日：2018-11-20
申请号：US15725752
申请日：2017-10-05
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chin-Han Meng , Chih-Hsien Hsu , Chia-Chi Chung , Yu-Pei Chiang , Wen-Chih Chen , Chen-Huang Huang , Zhi-Sheng Xu , Jr-Sheng Chen , Kuo-Chin Liu , Lin-Ching Huang
Abstract: A method for forming a micro-electro-mechanical system (MEMS) device structure is provided. The method includes forming a second substrate over a first substrate, and a cavity is formed between the first substrate and the second substrate. The method includes forming a hole through the second substrate using an etching process, and the hole is connected to the cavity. The etching process includes a plurality of etching cycles, and each of the etching cycles includes an etching step, and the etching step has a first stage and a second stage. The etching time of each of the etching steps during the second stage is gradually increased as the number of etching cycles is increased.
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公开(公告)号：US09997336B2
公开(公告)日：2018-06-12
申请号：US15138499
申请日：2016-04-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chin-Han Meng , Jr-Sheng Chen , Yin-Tun Chou , Chih-Hua Chan , Lin-Ching Huang , Yu-Pei Chiang
IPC: H01L21/67 , H01L21/82 , H01J37/32 , H01L21/66 , H01L21/3065 , H01L21/308 , H01L21/027
CPC classification number: H01J37/3244 , H01J37/32009 , H01J37/32449 , H01L21/0273 , H01L21/3065 , H01L21/3081 , H01L21/82 , H01L22/12
Abstract: A multi-zone gas distribution plate (GDP) for high uniformity in plasma-based etching is provided. A housing defines a process chamber and comprises a gas inlet configured to receive a process gas. A GDP is arranged in the process chamber and is configured to distribute the process gas within the process chamber. The GDP comprises a plurality of holes extending through the GDP, and further comprises a plurality of zones into which the holes are grouped. The zones comprise a first zone and a second zone. Holes of the first zone share a first cross-sectional profile and holes of the second zone share a second cross-sectional profile different than the first cross-sectional profile. A method for designing the multi-zone GDP is also provided.
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公开(公告)号：US10964547B2
公开(公告)日：2021-03-30
申请号：US16693389
申请日：2019-11-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chin-Han Meng , Chih-Hsien Hsu , Jr-Sheng Chen , An-Chi Li , Lin-Ching Huang , Yu-Pei Chiang
IPC: H01L21/3065 , B81C1/00 , H01L21/308 , H01L21/311
Abstract: A method of fabricating a semiconductor structure including the following steps is provided. A mask layer is formed on a semiconductor substrate. The semiconductor substrate revealed by the mask layer is anisotropically etched until a cavity is formed in the semiconductor substrate, wherein anisotropically etching the semiconductor substrate revealed by the mask layer comprises performing a plurality of first cycles and performing a plurality of second cycles after performing the first cycles, each cycle among the first and second cycles respectively includes performing a passivating step and performing an etching step after performing the passivating step. During the first cycles, a first duration ratio of the etching step to the passivating step is variable and ramps up step by step. During the second cycles, a second duration ratio of the etching step to the passivating step is constant, and the first duration ratio is less than the second duration ratio.
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公开(公告)号：US10529578B2
公开(公告)日：2020-01-07
申请号：US16175750
申请日：2018-10-30
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chin-Han Meng , Chih-Hsien Hsu , Jr-Sheng Chen , An-Chi Li , Lin-Ching Huang , Yu-Pei Chiang
IPC: H01L21/3065 , B81C1/00 , H01L21/308 , H01L21/311
Abstract: A method of fabricating a semiconductor structure including the following steps is provided. A mask layer is formed on a semiconductor substrate. The semiconductor substrate revealed by the mask layer is anisotropically etched until a cavity is formed in the semiconductor substrate, wherein anisotropically etching the semiconductor substrate revealed by the mask layer comprises performing a plurality of first cycles and performing a plurality of second cycles after performing the first cycles, each cycle among the first and second cycles respectively includes performing a passivating step and performing an etching step after performing the passivating step. During the first cycles, a first duration ratio of the etching step to the passivating step is variable and ramps up step by step. During the second cycles, a second duration ratio of the etching step to the passivating step is constant, and the first duration ratio is less than the second duration ratio.
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公开(公告)号：US10654713B2
公开(公告)日：2020-05-19
申请号：US16398091
申请日：2019-04-29
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chin-Han Meng , Jr-Sheng Chen , Chih-Hsien Hsu , Yu-Pei Chiang , Lin-Ching Huang
IPC: B81C1/00
Abstract: Methods for manufacturing MEMS structures are provided. The method for manufacturing a microelectromechanical system (MEMS) structure includes etching a MEMS substrate to form a first trench and a second trench and etching the MEMS substrate through the first trench and the second trench to form a first through hole and an extended second trench. The method for manufacturing a MEMS structure further includes etching the MEMS substrate through the extended second trench to form a second through hole. In addition, a height of the first trench is greater than ¾ of a height of the MEMS substrate, and a height of the second trench is smaller than ⅔ of the height of the MEMS substrate.
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Patent Agency Ranking
公开(公告)号：US20170309500A1
公开(公告)日：2017-10-26
申请号：US15138499
申请日：2016-04-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chin-Han Meng , Jr-Sheng Chen , Yin-Tun Chou , Chih-Hua Chan , Lin-Ching Huang , Yu-Pei Chiang
IPC: H01L21/67 , H01L21/82 , H01J37/32 , H01L21/027 , H01L21/3065 , H01L21/66 , H01L21/308
CPC classification number: H01J37/3244 , H01J37/32009 , H01J37/32449 , H01L21/0273 , H01L21/3065 , H01L21/3081 , H01L21/82 , H01L22/12
Abstract: A multi-zone gas distribution plate (GDP) for high uniformity in plasma-based etching is provided. A housing defines a process chamber and comprises a gas inlet configured to receive a process gas. A GDP is arranged in the process chamber and is configured to distribute the process gas within the process chamber. The GDP comprises a plurality of holes extending through the GDP, and further comprises a plurality of zones into which the holes are grouped. The zones comprise a first zone and a second zone. Holes of the first zone share a first cross-sectional profile and holes of the second zone share a second cross-sectional profile different than the first cross-sectional profile. A method for designing the multi-zone GDP is also provided.
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公开(公告)号：US10957516B2
公开(公告)日：2021-03-23
申请号：US15997914
申请日：2018-06-05
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chin-Han Meng , Jr-Sheng Chen , Yin-Tun Chou , Chih-Hua Chan , Lin-Ching Huang , Yu-Pei Chiang
IPC: H01J37/32 , H01L21/82 , H01L21/66 , H01L21/3065 , H01L21/308 , H01L21/027
Abstract: A multi-zone gas distribution plate (GDP) for high uniformity in plasma-based etching is provided. A housing defines a process chamber and comprises a gas inlet configured to receive a process gas. A GDP is arranged in the process chamber and is configured to distribute the process gas within the process chamber. The GDP comprises a plurality of holes extending through the GDP, and further comprises a plurality of zones into which the holes are grouped. The zones comprise a first zone and a second zone. Holes of the first zone share a first cross-sectional profile and holes of the second zone share a second cross-sectional profile different than the first cross-sectional profile. A method for designing the multi-zone GDP is also provided.
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公开(公告)号：US20190148161A1
公开(公告)日：2019-05-16
申请号：US16175750
申请日：2018-10-30
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chin-Han Meng , Chih-Hsien Hsu , Jr-Sheng Chen , An-Chi Li , Lin-Ching Huang , Yu-Pei Chiang
IPC: H01L21/3065 , H01L21/308 , B81C1/00
Abstract: A method of fabricating a semiconductor structure including the following steps is provided. A mask layer is formed on a semiconductor substrate. The semiconductor substrate revealed by the mask layer is anisotropically etched until a cavity is formed in the semiconductor substrate, wherein anisotropically etching the semiconductor substrate revealed by the mask layer comprises performing a plurality of first cycles and performing a plurality of second cycles after performing the first cycles, each cycle among the first and second cycles respectively includes performing a passivating step and performing an etching step after performing the passivating step. During the first cycles, a first duration ratio of the etching step to the passivating step is variable and ramps up step by step. During the second cycles, a second duration ratio of the etching step to the passivating step is constant, and the first duration ratio is less than the second duration ratio.
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公开(公告)号：US20250149302A1
公开(公告)日：2025-05-08
申请号：US18502485
申请日：2023-11-06
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chih-Kai Hu , Ren-Guan Duan , Chiun-Da Shiue , Chin-Han Meng
IPC: H01J37/32 , C23C16/40 , C23C16/455 , C23C28/04
Abstract: An anti-plasma coating formed on a surface of a component in a plasma chamber includes an insulation layer on the surface and a plasma-resistant layer on the insulation layer. The plasma-resistant layer includes one or more stacks, where each stack includes a crystalline layer and an amorphous layer. The anti-plasma coating improves a lifetime of the component in the plasma chamber with high-energy plasma sources.
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公开(公告)号：US20200098583A1
公开(公告)日：2020-03-26
申请号：US16693389
申请日：2019-11-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chin-Han Meng , Chih-Hsien Hsu , Jr-Sheng Chen , An-Chi Li , Lin-Ching Huang , Yu-Pei Chiang
IPC: H01L21/3065 , H01L21/308 , B81C1/00 , H01L21/311
Abstract: A method of fabricating a semiconductor structure including the following steps is provided. A mask layer is formed on a semiconductor substrate. The semiconductor substrate revealed by the mask layer is anisotropically etched until a cavity is formed in the semiconductor substrate, wherein anisotropically etching the semiconductor substrate revealed by the mask layer comprises performing a plurality of first cycles and performing a plurality of second cycles after performing the first cycles, each cycle among the first and second cycles respectively includes performing a passivating step and performing an etching step after performing the passivating step. During the first cycles, a first duration ratio of the etching step to the passivating step is variable and ramps up step by step. During the second cycles, a second duration ratio of the etching step to the passivating step is constant, and the first duration ratio is less than the second duration ratio.
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