公开(公告)号：US20240021469A1

公开(公告)日：2024-01-18

申请号：US18356843

申请日：2023-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ssu-Chiang Weng ,  Ping-Hao Lin ,  Fu-Cheng Chang

IPC: H01L21/768 ,  H01L25/065 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528 ,  H01L23/48 ,  H01L21/311

CPC classification number: H01L21/76832 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/76805 ,  H01L25/0657 ,  H01L21/76807 ,  H01L23/3171 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/481 ,  H01L21/31116

Abstract: A method includes bonding a first wafer to a second wafer. The first wafer includes a plurality of dielectric layers, a metal pipe penetrating through the plurality of dielectric layers, and a dielectric region encircled by the metal pipe. The dielectric region has a plurality of steps formed of sidewalls and top surfaces of portions of the plurality of dielectric layers that are encircled by the metal pipe. The method further includes etching the first wafer to remove the dielectric region and to leave an opening encircled by the metal pipe, extending the opening into the second wafer to reveal a metal pad in the second wafer, and filling the opening with a conductive material to form a conductive plug in the opening.

公开(公告)号：US11791205B2

公开(公告)日：2023-10-17

申请号：US17238496

申请日：2021-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ssu-Chiang Weng ,  Ping-Hao Lin ,  Fu-Cheng Chang

IPC: H01L25/065 ,  H01L23/522 ,  H01L21/768 ,  H01L23/31 ,  H01L23/528 ,  H01L23/48 ,  H01L21/311

CPC classification number: H01L21/76832 ,  H01L21/31116 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5283 ,  H01L25/0657

Abstract: A method includes bonding a first wafer to a second wafer. The first wafer includes a plurality of dielectric layers, a metal pipe penetrating through the plurality of dielectric layers, and a dielectric region encircled by the metal pipe. The dielectric region has a plurality of steps formed of sidewalls and top surfaces of portions of the plurality of dielectric layers that are encircled by the metal pipe. The method further includes etching the first wafer to remove the dielectric region and to leave an opening encircled by the metal pipe, extending the opening into the second wafer to reveal a metal pad in the second wafer, and filling the opening with a conductive material to form a conductive plug in the opening.

公开(公告)号：US20210098519A1

公开(公告)日：2021-04-01

申请号：US16994963

申请日：2020-08-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hsun Hsu ,  Ping-Hao Lin

IPC: H01L27/146

Abstract: In some embodiments, an image sensor is provided. The image sensor comprises a first photodetector disposed within a front-side surface of a semiconductor substrate. A trench isolation structure is disposed over a back-side surface of the semiconductor substrate. The trench isolation structure includes a buffer layer and a dielectric liner. The buffer layer covers the back-side surface of the semiconductor substrate and fills trenches that extend downward into the back-side surface of the semiconductor substrate. The dielectric liner is disposed between the buffer layer and the semiconductor substrate. A composite grid structure has composite grid segments that are aligned over the trenches, respectively. The buffer layer separates the dielectric liner from the composite grid structure. A light shield structure is disposed within the buffer layer and directly overlies the first photodetector.

公开(公告)号：US11764062B2

公开(公告)日：2023-09-19

申请号：US16175819

申请日：2018-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ping-Hao Lin ,  Fu-Cheng Chang

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/311 ,  G03F7/20 ,  G03F1/50 ,  G03F1/58 ,  G03F7/09 ,  G03F7/095 ,  H01L21/768 ,  G03F7/00

CPC classification number: H01L21/0337 ,  G03F1/50 ,  G03F1/58 ,  G03F7/094 ,  G03F7/095 ,  G03F7/70058 ,  G03F7/70466 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76807 ,  H01L2221/1021

Abstract: A method of forming a semiconductor structure is disclosed. A multi-layer structure is formed over a substrate. A photoresist stack with a stepped sidewall is formed on the multi-layer structure. A pattern of the photoresist stack is transferred to the multi-layer structure.

公开(公告)号：US11183523B2

公开(公告)日：2021-11-23

申请号：US16662453

申请日：2019-10-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Yu Wei ,  Hsin-Chi Chen ,  Kuo-Cheng Lee ,  Ping-Hao Lin ,  Hsun-Ying Huang ,  Yen-Liang Lin ,  Yu Ting Kao

IPC: H01L27/146

Abstract: The present disclosure relates to a CMOS image sensor, and an associated method of formation. In some embodiments, the CMOS image sensor comprises a floating diffusion region disposed at one side of a transfer gate within a substrate and a photo detecting column disposed at the other side of the transfer gate opposing to the floating diffusion region within the substrate. The photo detecting column comprises a doped sensing layer with a doping type opposite to that of the substrate. The photo detecting column and the substrate are in contact with each other at a junction interface comprising one or more recessed portions. By forming the junction interface with recessed portions, the junction interface is enlarged compared to a previous p-n junction interface without recessed portions, and thus a full well capacity of the photodiode structure is improved.

公开(公告)号：US10790321B2

公开(公告)日：2020-09-29

申请号：US16017078

申请日：2018-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Yu Wei ,  Hsin-Chi Chen ,  Kuo-Cheng Lee ,  Ping-Hao Lin ,  Hsun-Ying Huang ,  Yen-Liang Lin ,  Yu Ting Kao

IPC: H01L27/146

Abstract: The present disclosure relates to a CMOS image sensor, and an associated method of formation. In some embodiments, the CMOS image sensor comprises a floating diffusion region disposed at one side of a transfer gate within a substrate and a photo detecting column disposed at the other side of the transfer gate opposing to the floating diffusion region within the substrate. The photo detecting column comprises a doped sensing layer with a doping type opposite to that of the substrate. The photo detecting column and the substrate are in contact with each other at a junction interface comprising one or more recessed portions. By forming the junction interface with recessed portions, the junction interface is enlarged compared to a previous p-n junction interface without recessed portions, and thus a full well capacity of the photodiode structure is improved.

公开(公告)号：US12243772B2

公开(公告)日：2025-03-04

申请号：US18356843

申请日：2023-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ssu-Chiang Weng ,  Ping-Hao Lin ,  Fu-Cheng Chang

IPC: H01L23/522 ,  H01L21/311 ,  H01L21/768 ,  H01L23/31 ,  H01L23/48 ,  H01L23/528 ,  H01L25/065

Abstract: A method includes bonding a first wafer to a second wafer. The first wafer includes a plurality of dielectric layers, a metal pipe penetrating through the plurality of dielectric layers, and a dielectric region encircled by the metal pipe. The dielectric region has a plurality of steps formed of sidewalls and top surfaces of portions of the plurality of dielectric layers that are encircled by the metal pipe. The method further includes etching the first wafer to remove the dielectric region and to leave an opening encircled by the metal pipe, extending the opening into the second wafer to reveal a metal pad in the second wafer, and filling the opening with a conductive material to form a conductive plug in the opening.

公开(公告)号：US20210242080A1

公开(公告)日：2021-08-05

申请号：US17238496

申请日：2021-04-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ssu-Chiang Weng ,  Ping-Hao Lin ,  Fu-Cheng Chang

IPC: H01L21/768 ,  H01L25/065 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528 ,  H01L23/48 ,  H01L21/311

Abstract: A method includes bonding a first wafer to a second wafer. The first wafer includes a plurality of dielectric layers, a metal pipe penetrating through the plurality of dielectric layers, and a dielectric region encircled by the metal pipe. The dielectric region has a plurality of steps formed of sidewalls and top surfaces of portions of the plurality of dielectric layers that are encircled by the metal pipe. The method further includes etching the first wafer to remove the dielectric region and to leave an opening encircled by the metal pipe, extending the opening into the second wafer to reveal a metal pad in the second wafer, and filling the opening with a conductive material to form a conductive plug in the opening.

公开(公告)号：US20200058689A1

公开(公告)日：2020-02-20

申请号：US16662453

申请日：2019-10-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Yu Wei ,  Hsin-Chi Chen ,  Kuo-Cheng Lee ,  Ping-Hao Lin ,  Hsun-Ying Huang ,  Yen-Liang Lin ,  Yu Ting Kao

IPC: H01L27/146

Abstract: The present disclosure relates to a CMOS image sensor, and an associated method of formation. In some embodiments, the CMOS image sensor comprises a floating diffusion region disposed at one side of a transfer gate within a substrate and a photo detecting column disposed at the other side of the transfer gate opposing to the floating diffusion region within the substrate. The photo detecting column comprises a doped sensing layer with a doping type opposite to that of the substrate. The photo detecting column and the substrate are in contact with each other at a junction interface comprising one or more recessed portions. By forming the junction interface with recessed portions, the junction interface is enlarged compared to a previous p-n junction interface without recessed portions, and thus a full well capacity of the photodiode structure is improved.

公开(公告)号：US09842774B1

公开(公告)日：2017-12-12

申请号：US15180276

申请日：2016-06-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Lin Fang ,  Ping-Hao Lin ,  Ching-Hua Chu ,  Hsiao-Chun Lee ,  Chi-Feng Huang

IPC: H01L29/40 ,  H01L21/768 ,  H01L23/48 ,  H01L23/485 ,  H01L21/285 ,  H01L21/02 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76898 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/2855 ,  H01L21/76831 ,  H01L21/76843 ,  H01L23/481 ,  H01L23/485 ,  H01L23/5225 ,  H01L23/5286

Abstract: A semiconductor device includes a substrate and a through substrate via structure. The substrate has a through via hole. The through substrate via structure is disposed in the through via hole. The through substrate via structure disposed in the through via hole includes a liner structure and a metal layer. The liner structure includes at least two insulation liners and at least one conductive shielding layer disposed between the insulation liners, in which the insulation liners and the at least one conductive shielding layer conformally cover a sidewall and a bottom of the through via hole. The metal layer covers the liner structure and fills the through via hole.