公开(公告)号：US20240322010A1

公开(公告)日：2024-09-26

申请号：US18731945

申请日：2024-06-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chin Chang ,  Wei-Hao Wu ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/823431 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A method includes removing a dummy gate to leave a trench between gate spacers, forming a gate dielectric extending into the trench, depositing a metal layer over the gate dielectric, with the metal layer including a portion extending into the trench, depositing a filling region into the trench, with the metal layer have a first and a second vertical portion on opposite sides of the filling region, etching back the metal layer, with the filling region at least recessed less than the metal layer, and remaining parts of the portion of the metal layer forming a gate electrode, depositing a dielectric material into the trench, and performing a planarization to remove excess portions of the dielectric material. A portion of the dielectric material in the trench forms at least a portion of a dielectric hard mask over the gate electrode.

公开(公告)号：US11373902B2

公开(公告)日：2022-06-28

申请号：US16888929

申请日：2020-06-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Chang Sun ,  Po-Chin Chang ,  Akira Mineji ,  Zi-Wei Fang ,  Pinyen Lin

IPC: H01L21/768 ,  H01L21/8234 ,  H01L23/532 ,  H01L23/535 ,  H01L27/088

Abstract: A semiconductor structure includes a semiconductor substrate, a gate structure, an etch stop layer, a dielectric structure, and a conductive material. The gate structure is on the semiconductor substrate. The etch stop layer is over the gate structure. The dielectric structure is over the etch stop layer, in which the dielectric structure has a ratio of silicon to nitrogen varying from a middle layer of the dielectric structure to a bottom layer of the dielectric structure. The conductive material extends through the dielectric structure.

公开(公告)号：US11469143B2

公开(公告)日：2022-10-11

申请号：US17033256

申请日：2020-09-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Po-Chin Chang ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/768 ,  H01L29/78 ,  H01L23/522 ,  H01L21/3213

Abstract: A semiconductor device includes a semiconductor substrate, a source/drain region, a source/drain contact, a conductive via and a first polymer layer. The source/drain region is in the semiconductor substrate. The source/drain contact is over the source/drain region. The source/drain via is over the source/drain contact. The first polymer layer extends along a first sidewall of the conductive via and is separated from a second sidewall of the conductive via substantially perpendicular to the first sidewall of the conductive via.

公开(公告)号：US10707081B2

公开(公告)日：2020-07-07

申请号：US16178417

申请日：2018-11-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shih-Chun Huang ,  Chiu-Hsiang Chen ,  Ya-Wen Yeh ,  Yu-Tien Shen ,  Po-Chin Chang ,  Chien Wen Lai ,  Wei-Liang Lin ,  Ya Hui Chang ,  Yung-Sung Yen ,  Li-Te Lin ,  Pinyen Lin ,  Ru-Gun Liu ,  Chin-Hsiang Lin

IPC: H01L21/033 ,  H01L29/66 ,  H01L21/027 ,  H01L21/311 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3115

Abstract: A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.

公开(公告)号：US12087558B2

公开(公告)日：2024-09-10

申请号：US17402030

申请日：2021-08-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Hao Chang ,  Po-Chin Chang ,  Pinyen Lin ,  Li-Te Lin

IPC: H01J37/32 ,  H01L21/263 ,  H01L21/687

CPC classification number: H01J37/32651 ,  H01J37/32422 ,  H01J37/32733 ,  H01L21/2633 ,  H01L21/68764 ,  H01J2237/334

Abstract: The present disclosure relates to a semiconductor device manufacturing system. The semiconductor device manufacturing system can include a chamber and an ion source in the chamber. The ion source can include an outlet. The ion source can be configured to generate a particle beam. The semiconductor device manufacturing system can further include a grid structure proximate to the outlet of the ion source and configured to manipulate the particle beam. A first portion of the grid structure can be electrically insulated from a second portion of the grid structure.

公开(公告)号：US20230155005A1

公开(公告)日：2023-05-18

申请号：US17663278

申请日：2022-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Hao-Heng Liu ,  Po-Chin Chang ,  Yi-Shan Chen ,  Ming-Huan Tsai

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/417 ,  H01L27/088

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L29/7851 ,  H01L21/823481 ,  H01L21/823418 ,  H01L29/41791 ,  H01L27/0886

Abstract: A method includes forming a first fin and a second fin protruding from a substrate; forming an isolation layer surrounding the first fin and the second fin; epitaxially growing a first epitaxial region on the first fin and a second epitaxial region on the second fin, wherein the first epitaxial region and the second epitaxial region are merged together; performing an etching process on the first epitaxial region and the second epitaxial region, wherein the etching process separates the first epitaxial region from the second epitaxial region; depositing a dielectric material between the first epitaxial region and the second epitaxial region; and forming a first gate stack extending over the first fin.

公开(公告)号：US11626506B2

公开(公告)日：2023-04-11

申请号：US17306316

申请日：2021-05-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chin Chang ,  Wei-Hao Wu ,  Li-Te Lin ,  Pinyen Lin

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/49

Abstract: A method includes removing a dummy gate to leave a trench between gate spacers, forming a gate dielectric extending into the trench, depositing a metal layer over the gate dielectric, with the metal layer including a portion extending into the trench, depositing a filling region into the trench, with the metal layer have a first and a second vertical portion on opposite sides of the filling region, etching back the metal layer, with the filling region at least recessed less than the metal layer, and remaining parts of the portion of the metal layer forming a gate electrode, depositing a dielectric material into the trench, and performing a planarization to remove excess portions of the dielectric material. A portion of the dielectric material in the trench forms at least a portion of a dielectric hard mask over the gate electrode.

公开(公告)号：US20230029002A1

公开(公告)日：2023-01-26

申请号：US17577707

申请日：2022-01-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chin Chang ,  Lin-Yu Huang ,  Shuen-Shin Liang ,  Sheng-Tsung Wang ,  Cheng-Chi Chuang ,  Chia-Hung Chu ,  Tzu Pei Chen ,  Yuting Cheng ,  Sung-Li Wang

IPC: H01L21/768 ,  H01L23/535

Abstract: The present disclosure describes a semiconductor device with a nitrided capping layer and methods for forming the same. One method includes forming a first conductive structure in a first dielectric layer on a substrate, depositing a second dielectric layer on the first conductive structure and the first dielectric layer, and forming an opening in the second dielectric layer to expose the first conductive structure and a portion of the first dielectric layer. The method further includes forming a nitrided layer on a top portion of the first conductive structure, a top portion of the portion of the first dielectric layer, sidewalls of the opening, and a top portion of the second dielectric layer, and forming a second conductive structure in the opening, where the second conductive structure is in contact with the nitrided layer.

公开(公告)号：US11043381B2

公开(公告)日：2021-06-22

申请号：US16258656

申请日：2019-01-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chin Chang ,  Li-Te Lin ,  Ru-Gun Liu ,  Wei-Liang Lin ,  Pinyen Lin ,  Yu-Tien Shen ,  Ya-Wen Yeh

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H01L21/02

Abstract: A directional patterning method includes following steps. A substrate is provided with a mask layer thereon, and the mask layer has at least one opening pattern therein. A cyclic deposition and etching process is performed to increase a length of the at least one opening pattern.

公开(公告)号：US20200243336A1

公开(公告)日：2020-07-30

申请号：US16258656

申请日：2019-01-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chin Chang ,  Li-Te Lin ,  Ru-Gun Liu ,  Wei-Liang Lin ,  Pinyen Lin ,  Yu-Tien Shen ,  Ya-Wen Yeh

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/02 ,  H01L21/768

Abstract: A directional patterning method includes following steps. A substrate is provided with a mask layer thereon, and the mask layer has at least one opening pattern therein. A cyclic deposition and etching process is performed to increase a length of the at least one opening pattern.