公开(公告)号：US20190165167A1

公开(公告)日：2019-05-30

申请号：US16173721

申请日：2018-10-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Chou LIN ,  Yi-Cheng CHIU ,  Karthick MURUKESAN ,  Yi-Min CHEN ,  Shiuan-Jeng LIN ,  Wen-Chih CHIANG ,  Chen-Chien CHANG ,  Chih-Yuan CHAN ,  Kuo-Ming WU ,  Chun-Lin TSAI

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/40

Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.

公开(公告)号：US20190157378A1

公开(公告)日：2019-05-23

申请号：US15940075

申请日：2018-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Guo-Jyun LUO ,  Shiuan-Jeng LIN ,  Chiu-Hua CHUNG ,  Chen-Chien CHANG ,  Han-Zong PAN

IPC: H01L49/02 ,  H01L27/06 ,  H01L21/285

Abstract: A semiconductor device structure and the formation method thereof are provided. The semiconductor device structure includes a semiconductor substrate and a first capacitor and a second capacitor over the semiconductor substrate. The first capacitor has a first capacitor dielectric layer, and the second capacitor has a second capacitor dielectric layer. The first capacitor dielectric layer is between the second capacitor dielectric layer and the semiconductor substrate. The first capacitor and the second capacitor are electrically connected in parallel. The first capacitor has a first linear temperature coefficient and a first quadratic voltage coefficient. The second capacitor has a second linear temperature coefficient and a second quadratic voltage coefficient. One or both of a first ratio of the first linear temperature coefficient to the second linear temperature coefficient and a second ratio of the first quadratic voltage coefficient to the second quadratic voltage coefficient is negative.

公开(公告)号：US20240363495A1

公开(公告)日：2024-10-31

申请号：US18767848

申请日：2024-07-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Jung CHEN ,  Cheng-Hung WANG ,  Tsung-Lin LEE ,  Shiuan-Jeng LIN ,  Chun-Ming LIN ,  Wen-Chih CHIANG

IPC: H01L23/48 ,  H01L21/02 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/58 ,  H01L29/06

CPC classification number: H01L23/481 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/31116 ,  H01L21/76283 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53271 ,  H01L23/585 ,  H01L29/0649

Abstract: Structures and methods for reducing process charging damages are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a polysilicon region and an etch stop layer. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, and a buried layer arranged over the insulation layer. The polysilicon region extends downward from an upper surface of the buried layer and terminates in the handle layer. The etch stop layer is located on the substrate. The etch stop layer is in contact with both the substrate and the polysilicon region.