公开(公告)号：US12114496B2

公开(公告)日：2024-10-08

申请号：US18225561

申请日：2023-07-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han Lin ,  Te-An Chen

IPC: H10B41/27 ,  H01L21/033 ,  H01L29/06 ,  H10B43/27

CPC classification number: H10B41/27 ,  H01L21/0337 ,  H01L29/0649 ,  H10B43/27

Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

公开(公告)号：US20210083042A1

公开(公告)日：2021-03-18

申请号：US17106409

申请日：2020-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu ,  Te-An Chen

IPC: H01L49/02 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/08

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has a substrate having an isolation structure therein and a capacitor structure located on an upper top surface of the isolation structure. The capacitor structure comprises a first semiconductor structure and a second semiconductor structure respectively disposed on the upper surface of the isolation structure and separated by an insulator pattern.

公开(公告)号：US11532694B2

公开(公告)日：2022-12-20

申请号：US17106409

申请日：2020-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-Hsin Chiu ,  Wei Cheng Wu ,  Te-An Chen

IPC: H01L49/02 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/08 ,  H01L23/64 ,  H01L29/92 ,  H01L21/28 ,  H01L21/3115 ,  H01L21/3215 ,  H01L21/768

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has a substrate having an isolation structure therein and a capacitor structure located on an upper top surface of the isolation structure. The capacitor structure comprises a first semiconductor structure and a second semiconductor structure respectively disposed on the upper surface of the isolation structure and separated by an insulator pattern.

公开(公告)号：US20210335782A1

公开(公告)日：2021-10-28

申请号：US16859992

申请日：2020-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-An Chen

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234

Abstract: Provided is a semiconductor device including a substrate, an isolation structure, a gate dielectric layer, a high-k dielectric layer, and a protection cap. The substrate includes a first region, a second region, and a transition region located between the first region and the second region. The isolation structure, located in the transition region. The gate dielectric layer is located on the isolation structure. The high-k dielectric layer is located on the isolation structure and extended to cover a sidewall and a surface of the gate dielectric layer. The protection cap is located on a surface and sidewalls of the high-k dielectric layer.

公开(公告)号：US20230371251A1

公开(公告)日：2023-11-16

申请号：US18225561

申请日：2023-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han LIN ,  Te-An Chen

IPC: H10B41/27 ,  H01L21/033 ,  H01L29/06 ,  H10B43/27

CPC classification number: H10B41/27 ,  H01L21/0337 ,  H01L29/0649 ,  H10B43/27

Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

公开(公告)号：US11778815B2

公开(公告)日：2023-10-03

申请号：US17833834

申请日：2022-06-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han Lin ,  Te-An Chen

IPC: H10B41/27 ,  H01L21/033 ,  H01L29/06 ,  H10B43/27

CPC classification number: H10B41/27 ,  H01L21/0337 ,  H01L29/0649 ,  H10B43/27

Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

公开(公告)号：US11515212B2

公开(公告)日：2022-11-29

申请号：US16938875

申请日：2020-07-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Te-An Chen ,  Meng-Han Lin

IPC: H01L21/8234 ,  H01L27/092 ,  H01L29/08 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L21/8238 ,  H01L21/786 ,  H01L21/28 ,  H01L27/088

Abstract: In a method of manufacturing a semiconductor device, an isolation structure is formed in a substrate defining an active region, a first gate structure is formed over the isolation structure and a second gate structure over the active region adjacent to the first gate structure, a cover layer is formed to cover the first gate structure and a part of the active region between the first gate structure and the second gate structure, the active region between the first gate structure and the second gate structure not covered by the cover layer is etched to form a recess, and an epitaxial semiconductor layer is formed in the recess.

公开(公告)号：US11450660B2

公开(公告)日：2022-09-20

申请号：US16859992

申请日：2020-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-An Chen

IPC: H01L29/76 ,  H01L29/94 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/423

Abstract: Provided is a semiconductor device including a substrate, an isolation structure, a gate dielectric layer, a high-k dielectric layer, and a protection cap. The substrate includes a first region, a second region, and a transition region located between the first region and the second region. The isolation structure, located in the transition region. The gate dielectric layer is located on the isolation structure. The high-k dielectric layer is located on the isolation structure and extended to cover a sidewall and a surface of the gate dielectric layer. The protection cap is located on a surface and sidewalls of the high-k dielectric layer.

公开(公告)号：US11355507B2

公开(公告)日：2022-06-07

申请号：US16887749

申请日：2020-05-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han Lin ,  Te-An Chen

IPC: H01L27/11556 ,  H01L21/033 ,  H01L29/06 ,  H01L27/11582

Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

公开(公告)号：US20210343704A1

公开(公告)日：2021-11-04

申请号：US16861215

申请日：2020-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Te-An Chen

IPC: H01L27/06 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/417

Abstract: A semiconductor device includes a substrate having a first region and a second region, a first gate structure disposed on the substrate within the first region, a first S/D region, a first S/D contact, a second gate structure on the substrate within the second region, a second S/D region and a second S/D contact. The first S/D region is disposed in the substrate within the first region and beside the first gate structure. The first S/D contact is connected to the first S/D region. The second S/D region is disposed in the substrate within the second region and beside the second gate structure. The second S/D contact is connected to the second S/D region. The contact area between the second S/D region and the second S/D contact is larger than a contact area between the first S/D region and the first S/D contact.