公开(公告)号：US20190326310A1

公开(公告)日：2019-10-24

申请号：US16291347

申请日：2019-03-04

Applicant: Toshiba Memory Corporation

Inventor： Yoshiaki FUKUZUMI ,  Keisuke SUDA ,  Fumiki AISO ,  Atsushi FUKUMOTO

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/06 ,  G11C16/04

Abstract: A semiconductor memory includes a substrate, a source line layer above the substrate in a memory region and a peripheral region of the substrate, a first insulating layer above the source line layer, a first conductive layer on the first insulating layer in the memory and peripheral regions, an alternating stack of a plurality of second insulating layers and a plurality of second conductive layers on the first conductive layer in the memory region, and a plurality of pillars extending through the alternating stack of the second insulating layers and the second conductive layers, the first conductive layer, and the first insulating layer in the memory region. A bottom end of each of the pillars is in the source line layer in a thickness direction. A carrier density of the source line layer is higher in the memory region than in the peripheral region.

公开(公告)号：US20220077170A1

公开(公告)日：2022-03-10

申请号：US17524984

申请日：2021-11-12

Applicant: Toshiba Memory Corporation

Inventor： Yoshiaki FUKUZUMI ,  Keisuke SUDA ,  Fumiki AISO ,  Atsushi FUKUMOTO

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C16/04 ,  G11C5/06

Abstract: A semiconductor memory includes a substrate, a source line layer above the substrate in a memory region and a peripheral region of the substrate, a first insulating layer above the source line layer, a first conductive layer on the first insulating layer in the memory and peripheral regions, an alternating stack of a plurality of second insulating layers and a plurality of second conductive layers on the first conductive layer in the memory region, and a plurality of pillars extending through the alternating stack of the second insulating layers and the second conductive layers, the first conductive layer, and the first insulating layer in the memory region. A bottom end of each of the pillars is in the source line layer in a thickness direction. A carrier density of the source line layer is higher in the memory region than in the peripheral region.

公开(公告)号：US20180083028A1

公开(公告)日：2018-03-22

申请号：US15459319

申请日：2017-03-15

Applicant: Toshiba Memory Corporation

Inventor： Atsushi FUKUMOTO ,  Fumiki AISO ,  Hajime NAGANO ,  Takuo OHASHI

IPC: H01L27/11582 ,  H01L29/04 ,  H01L29/10 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/311 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02667 ,  H01L21/3065 ,  H01L21/31116 ,  H01L27/11556 ,  H01L29/04 ,  H01L29/1037 ,  H01L29/1041

Abstract: According to one embodiment, a semiconductor device includes a foundation layer, a stacked body provided on the foundation layer, the stacked body including a plurality of electrode layers stacked with an insulator interposed, a semiconductor body extending through the stacked body in a stacking direction of the stacked body, and a charge storage portion provided between the semiconductor body and the electrode layers. The semiconductor body includes a first semiconductor film, and a second semiconductor film provided between the first semiconductor film and the charge storage portion. An average grain size of a crystal of the second semiconductor film is larger than an average grain size of a crystal of the first semiconductor film.

公开(公告)号：US20180006053A1

公开(公告)日：2018-01-04

申请号：US15703006

申请日：2017-09-13

Applicant: Toshiba Memory Corporation

Inventor： Takuo OHASHI ,  Fumiki AISO

IPC: H01L27/11582 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L27/11556

Abstract: According to an embodiment, a semiconductor memory device includes a plurality of control gate electrodes, a semiconductor layer, and a charge accumulation layer. The plurality of control gate electrodes are provided as a stack above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The charge accumulation layer is positioned between the control gate electrode and the semiconductor layer. A lower end of the charge accumulation layer is positioned more upwardly than a lower end of a lowermost layer-positioned one of the control gate electrodes.

公开(公告)号：US20190071771A1

公开(公告)日：2019-03-07

申请号：US15919268

申请日：2018-03-13

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Fumiki AISO ,  Kensei TAKAHASHI ,  Tomohisa IINO

IPC: C23C16/44 ,  H01L21/02 ,  C23C16/34 ,  C23C16/455 ,  C23C16/56

Abstract: According to an embodiment, a semiconductor manufacturing apparatus includes a chamber, a process gas nozzle, an inert gas nozzle and a hydrogen radical nozzle. The chamber houses at least one substrate. The process gas nozzle is to release process gas toward the substrate in the chamber. The inert gas nozzle is to release inert gas toward the substrate in the chamber. The hydrogen radical nozzle is disposed in the chamber and is to generate hydrogen radicals by heating raw material gas including hydrogen and to release the generated hydrogen radicals toward the substrate during the release of the inert gas. A metal wire is in the hydrogen radical nozzle, and the metal wire includes a metal catalyst for exciting the generation of the hydrogen radicals.

公开(公告)号：US20190067066A1

公开(公告)日：2019-02-28

申请号：US15915792

申请日：2018-03-08

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Fumiki AISO ,  Ryota FUJITSUKA ,  Kensei TAKAHASHI ,  Takayuki MATSUI ,  Tomohisa IINO

IPC: H01L21/677 ,  H01L21/687 ,  H01L21/67 ,  H01L21/673 ,  B25J11/00 ,  B25J15/00

CPC classification number: H01L21/67745 ,  B25J11/0095 ,  B25J15/0014 ,  C23C16/44 ,  H01L21/67017 ,  H01L21/67303 ,  H01L21/67309 ,  H01L21/67313 ,  H01L21/67748 ,  H01L21/68707

Abstract: In one embodiment, a semiconductor manufacturing apparatus includes a container to contain wafers, and supporting tables provided in the container so as to be stacked on one another, and each including a supporting face that comes into contact with a wafer to support the wafer. The apparatus further includes supporting columns to join the supporting tables together and provided at positions where the supporting columns are contained inside outer circumferences of the supporting tables. The apparatus further includes a gas feeder to feed a gas to the wafers on the supporting tables, and a gas discharger to discharge the gas fed to the wafers on the supporting tables. Each of the supporting tables includes a first upper face as the supporting face, and a second upper face provided so as to surround the first upper face at a level higher than a level of the first upper face.

公开(公告)号：US20180277400A1

公开(公告)日：2018-09-27

申请号：US15699222

申请日：2017-09-08

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Fumiki AISO

IPC: H01L21/67 ,  C23C16/455 ,  C23C16/52 ,  C23C16/46

CPC classification number: H01L21/67017 ,  C23C16/45544 ,  C23C16/45578 ,  C23C16/46 ,  C23C16/52 ,  C23C16/54 ,  H01L21/6719 ,  H01L21/67201

Abstract: According to an embodiment, a semiconductor manufacturing apparatus includes a process chamber, a load lock chamber, a gas purge mechanism and a movement mechanism. The process chamber treats a substrate using process gas in a vacuum state. The load lock chamber temporarily houses the substrate while holding the vacuum state. The gas purge mechanism is in the process chamber or the load lock chamber. The movement mechanism retains the substrate below the gas purge mechanism. The gas purge mechanism includes a plurality of gas feed ports opposing to the movement mechanism and to eject inactive gas at a first pressure higher than an atmospheric pressure, and a plurality of gas discharge ports provided alternately along with the plurality of gas feed ports along a movement direction of the movement mechanism and to discharge the process gas and the inactive gas at a second pressure lower than the atmospheric pressure.