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    Method of fabricating element including nanogap electrodes
    5.
    发明授权
    Method of fabricating element including nanogap electrodes 有权
    制造纳米胶片电极元件的方法

    公开(公告)号：US09130159B2

    公开(公告)日：2015-09-08

    申请号：US12756522

    申请日：2010-04-08

    申请人： Shigeo Furuta ,  Touru Sumiya ,  Yuichiro Masuda ,  Tsuyoshi Takahashi ,  Yutaka Hayashi ,  Masatoshi Ono

    发明人： Shigeo Furuta ,  Touru Sumiya ,  Yuichiro Masuda ,  Tsuyoshi Takahashi ,  Yutaka Hayashi ,  Masatoshi Ono

    IPC分类号： H01H11/00 ,  H01H65/00 ,  H01L45/00

    CPC分类号： H01L45/1233 ,  H01L45/04 ,  H01L45/16 ,  Y10T29/49082 ,  Y10T29/49105

    摘要： Disclosed is a fabrication method of an element with nanogap electrodes including a first electrode, a second electrode provided above the first electrode, and a gap provided between the first electrode and the second electrode, the gap being in an order of nanometer to allow resistive state to be switched by applying a predetermined voltage between the first electrode and the second electrode, the method comprising: forming the first electrode; forming a spacer on an upper surface of the first electrode; forming the second electrode in contact with an upper surface of the spacer; and removing the spacer to form the gap.

    摘要翻译： 公开了一种具有纳米隙电极的元件的制造方法，其包括第一电极，设置在第一电极上方的第二电极和设置在第一电极和第二电极之间的间隙，间隙为纳米级，以允许电阻状态 通过在第一电极和第二电极之间施加预定电压进行切换，该方法包括：形成第一电极; 在所述第一电极的上表面上形成间隔物; 形成与间隔物的上表面接触的第二电极; 并移除间隔物以形成间隙。

    Memory cell array
    8.
    发明授权
    Memory cell array 有权
    存储单元阵列

    公开(公告)号：US08174871B2

    公开(公告)日：2012-05-08

    申请号：US12644608

    申请日：2009-12-22

    申请人： Tsuyoshi Takahashi ,  Yutaka Hayashi ,  Yuichiro Masuda ,  Shigeo Furuta ,  Masatoshi Ono

    发明人： Tsuyoshi Takahashi ,  Yutaka Hayashi ,  Yuichiro Masuda ,  Shigeo Furuta ,  Masatoshi Ono

    IPC分类号： G11C11/00

    CPC分类号： H01L27/24 ,  G11C13/00 ,  G11C13/0069 ,  G11C13/02 ,  G11C2013/0071 ,  G11C2013/009 ,  G11C2213/79

    摘要： Disclosed is a memory cell array including word and first bit lines and second bit lines respectively connected to memory cells, wherein each memory cell includes a MOS transistor and switching element having first and second conductive layers and a gap in which a resistance value changes by applying a predetermined voltage, and data is written by specifying the first bit line to connect it to a ground, specifying the word line and supplying a write voltage to the second bit lines, and read by specifying the word line, and specifying the first bit line to supply a read voltage lower than the write voltage to the second bit lines, and the word line is specified when the voltage of the word line becomes a gate threshold value voltage or more and a sum of a drive voltage and the gate threshold value voltage or less.

    摘要翻译： 公开了一种存储单元阵列，包括分别连接到存储单元的单词和第一位线和第二位线，其中每个存储单元包括MOS晶体管和具有第一和第二导电层的开关元件以及通过施加电阻值而改变电阻值的间隙 通过指定第一位线将其连接到地，写入数据，指定字线并向第二位线提供写入电压，并通过指定字线进行读取，并指定第一位线 以向第二位线提供低于写入电压的读取电压，并且当字线的电压变为栅极阈值电压以上并且驱动电压和栅极阈值电压之和时，指定字线 或更少。

    Memory cell array
    9.
    发明授权
    Memory cell array 有权
    存储单元阵列

    公开(公告)号：US08094484B2

    公开(公告)日：2012-01-10

    申请号：US12644851

    申请日：2009-12-22

    申请人： Tsuyoshi Takahashi ,  Yutaka Hayashi ,  Yuichiro Masuda ,  Shigeo Furuta ,  Masatoshi Ono

    发明人： Tsuyoshi Takahashi ,  Yutaka Hayashi ,  Yuichiro Masuda ,  Shigeo Furuta ,  Masatoshi Ono

    IPC分类号： G11C11/00

    CPC分类号： H01L27/24 ,  G11C13/00 ,  G11C13/0069 ,  G11C13/02 ,  G11C2013/0071 ,  G11C2013/009 ,  G11C2213/79

    摘要： Disclosed is a memory cell array including word and first bit lines and second bit lines respectively connected to memory cells, wherein each memory cell includes a MOS transistor and switching element having first and second conductive layers and a gap in which a resistance value changes by applying a predetermined voltage, and data is written by specifying the first bit line to connect it to a ground, specifying the word line and supplying a write voltage to the second bit lines, and read by specifying the first bit line to connect it to the sense amplifier, specifying the word line and supplying a read voltage lower than the write voltage to the second bit lines, and the word line is specified when the word line voltage becomes a gate threshold value voltage or more and a sum of a drive voltage and the gate threshold value voltage or less.

    摘要翻译： 公开了一种存储单元阵列，包括分别连接到存储单元的单词和第一位线和第二位线，其中每个存储单元包括MOS晶体管和具有第一和第二导电层的开关元件以及通过施加电阻值而改变电阻值的间隙 通过指定第一位线将其连接到地，写入数据，指定字线并向第二位线提供写入电压，并通过指定第一位线将其连接到感测来读取 放大器，指定字线并将低于写入电压的读取电压提供给第二位线，并且当字线电压变为栅极阈值电压或更高时指定字线，并且驱动电压和 门极阈值电压以下。

    Memory Cell Array
    10.
    发明申请
    Memory Cell Array 有权
    存储单元阵列

    公开(公告)号：US20100165696A1

    公开(公告)日：2010-07-01

    申请号：US12644608

    申请日：2009-12-22

    申请人： Tsuyoshi Takahashi ,  Yutaka Hayashi ,  Yuichiro Masuda ,  Shigeo Furuta ,  Masatoshi Ono

    发明人： Tsuyoshi Takahashi ,  Yutaka Hayashi ,  Yuichiro Masuda ,  Shigeo Furuta ,  Masatoshi Ono

    IPC分类号： G11C5/06 ,  G11C7/00

    CPC分类号： H01L27/24 ,  G11C13/00 ,  G11C13/0069 ,  G11C13/02 ,  G11C2013/0071 ,  G11C2013/009 ,  G11C2213/79

    摘要： Disclosed is a memory cell array including word and first bit lines and second bit lines respectively connected to memory cells, wherein each memory cell includes a MOS transistor and switching element having first and second conductive layers and a gap in which a resistance value changes by applying a predetermined voltage, and data is written by specifying the first bit line to connect it to a ground, specifying the word line and supplying a write voltage to the second bit lines, and read by specifying the word line, and specifying the first bit line to supply a read voltage lower than the write voltage to the second bit lines, and the word line is specified when the voltage of the word line becomes a gate threshold value voltage or more and a sum of a drive voltage and the gate threshold value voltage or less.

    摘要翻译： 公开了一种存储单元阵列，包括分别连接到存储单元的单词和第一位线和第二位线，其中每个存储单元包括MOS晶体管和具有第一和第二导电层的开关元件以及通过施加电阻值而改变电阻值的间隙 通过指定第一位线将其连接到地，写入数据，指定字线并向第二位线提供写入电压，并通过指定字线进行读取，并指定第一位线 以向第二位线提供低于写入电压的读取电压，并且当字线的电压变为栅极阈值电压以上并且驱动电压和栅极阈值电压之和时，指定字线 或更少。