公开(公告)号：US20190080968A1

公开(公告)日：2019-03-14

申请号：US15700175

申请日：2017-09-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Yi Wang ,  Tien-Shan Hsu ,  Yu-Chih Su ,  Chi-Hsuan Cheng ,  Cheng-Pu Chiu ,  Te-Chang Hsu ,  Chin-Yang Hsieh ,  An-Chi Liu ,  Kuan-Lin Chen ,  Yao-Jhan Wang

IPC: H01L21/8234 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/762

Abstract: A method of fabricating fins includes providing a silicon substrate. The silicon substrate is etched to form numerous fin elements. A surface of each of the fin elements is silicon. Etch residues are formed on the fin elements after the silicon substrate is etched. After that, a flush step is performed on the fin elements by flushing the surface of each of the fin elements with fluorocarbons. The etch residues on the fin elements are removed by the flush step. After the flush step, a strip step is performed on the fin elements by treating the surface of each of the fin elements with oxygen plasma.

公开(公告)号：US20190027603A1

公开(公告)日：2019-01-24

申请号：US15696201

申请日：2017-09-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Hsuan Cheng ,  Cheng-Pu Chiu ,  Yu-Chih Su ,  Chih-Yi Wang ,  Chin-Yang Hsieh ,  Tien-Shan Hsu ,  Yao-Jhan Wang

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a first and a second fin structures, a first, a second and a third isolation structures, and a first and a second gate structures. The first and second fin structures are disposed in a substrate. The first isolation structure is disposed in the substrate and surrounds the first and second fin structures. The second isolation structure is disposed in the first fin structure, and a top surface of the second isolation structure is leveled with a top surface of the first and second fin structures. The third isolation structure is disposed in the second fin shaped structure, and a top surface of the third isolation structure is lower than the top surface of the first and second fin structures. The first and second gate structures are disposed on the second and third isolation structures, respectively.

公开(公告)号：US20190148550A1

公开(公告)日：2019-05-16

申请号：US16244076

申请日：2019-01-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Hsuan Cheng ,  Cheng-Pu Chiu ,  Yu-Chih Su ,  Chih-Yi Wang ,  Chin-Yang Hsieh ,  Tien-Shan Hsu ,  Yao-Jhan Wang

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L29/7846 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0653

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a first and a second fin structures, a first, a second and a third isolation structures, and a first and a second gate structures. The first and second fin structures are disposed in a substrate. The first isolation structure is disposed in the substrate and surrounds the first and second fin structures. The second isolation structure is disposed in the first fin structure, and a top surface of the second isolation structure is leveled with a top surface of the first and second fin structures. The third isolation structure is disposed in the second fin shaped structure, and a top surface of the third isolation structure is lower than the top surface of the first and second fin structures. The first and second gate structures are disposed on the second and third isolation structures, respectively.

公开(公告)号：US20230337551A1

公开(公告)日：2023-10-19

申请号：US17743459

申请日：2022-05-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jia-Rong Wu ,  Chi-Hsuan Cheng ,  Rai-Min Huang ,  Po-Kai Hsu

IPC: H01L43/14 ,  H01L27/22 ,  H01L43/04 ,  H01L43/06

CPC classification number: H01L43/14 ,  H01L27/222 ,  H01L43/04 ,  H01L43/06

Abstract: A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) on a substrate, forming a first spin orbit torque (SOT) layer on the MTJ, forming an inter-metal dielectric (IMD) layer around the first SOT layer, forming a second SOT layer on the IMD layer, forming a first hard mask on the second SOT layer, patterning the first hard mask along a first direction, and then patterning the first hard mask along a second direction.

公开(公告)号：US20210273089A1

公开(公告)日：2021-09-02

申请号：US17321517

申请日：2021-05-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Wei Su ,  Hao-Hsuan Chang ,  Chih-Wei Chang ,  Chi-Hsuan Cheng ,  Ting-An Chien ,  Bin-Siang Tsai

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/66 ,  H01L21/768

Abstract: A semiconductor device includes a substrate having at least two fins thereon and an isolation trench between the at least two fins; and an isolation structure in the isolation trench. The isolation structure consists of a liner layer covering a lower sidewall of each of the at least two fins and a bottom surface of the isolation trench, and a stress-buffer film on the liner layer. The stress-buffer film is a silicon suboxide film of formula SiOy, wherein y

公开(公告)号：US20190103492A1

公开(公告)日：2019-04-04

申请号：US15722801

申请日：2017-10-02

Applicant: United Microelectronics Corp.

Inventor： Cheng-Pu Chiu ,  Pei-Yu Chen ,  Shih-Min Lu ,  Ming-Yueh Tsai ,  Yung-Sung Lin ,  Te-Chang Hsu ,  Chih-Yi Wang ,  Chi-Hsuan Cheng ,  Sheng-Chen Chung ,  Yao-Jhan Wang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66 ,  H01L21/02

Abstract: A method for forming epitaxial material on base material includes forming a stress cap layer on a base layer of a first semiconductor material. Then, a stress is induced on the base layer, wherein the stress is a tensile stress or a compressive stress. The stress cap layer is removed. An epitaxial layer of a second semiconductor material is formed on the base layer, wherein the second semiconductor material is different from the first semiconductor material.

公开(公告)号：US10446682B2

公开(公告)日：2019-10-15

申请号：US16244076

申请日：2019-01-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chi-Hsuan Cheng ,  Cheng-Pu Chiu ,  Yu-Chih Su ,  Chih-Yi Wang ,  Chin-Yang Hsieh ,  Tien-Shan Hsu ,  Yao-Jhan Wang

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a first and a second fin structures, a first, a second and a third isolation structures, and a first and a second gate structures. The first and second fin structures are disposed in a substrate. The first isolation structure is disposed in the substrate and surrounds the first and second fin structures. The second isolation structure is disposed in the first fin structure, and a top surface of the second isolation structure is leveled with a top surface of the first and second fin structures. The third isolation structure is disposed in the second fin shaped structure, and a top surface of the third isolation structure is lower than the top surface of the first and second fin structures. The first and second gate structures are disposed on the second and third isolation structures, respectively.

公开(公告)号：US10283415B2

公开(公告)日：2019-05-07

申请号：US16132460

申请日：2018-09-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Te-Chang Hsu ,  An-Chi Liu ,  Nan-Yuan Huang ,  Yu-Chih Su ,  Cheng-Pu Chiu ,  Tien-Shan Hsu ,  Chih-Yi Wang ,  Chi-Hsuan Cheng

IPC: H01L21/8234 ,  H01L21/308 ,  H01L21/762

Abstract: A semiconductor structure includes a substrate, a plurality of fin shaped structures, a trench, and a first bump. The substrate has a base, and the fin shaped structures protrude from the base. The trench is recessed from the base of the substrate. The first bump is disposed within the trench and protrudes from a bottom surface of the trench. A width of the first bump is larger than a width of each of the fin shaped structures.

公开(公告)号：US10211107B1

公开(公告)日：2019-02-19

申请号：US15700175

申请日：2017-09-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Yi Wang ,  Tien-Shan Hsu ,  Yu-Chih Su ,  Chi-Hsuan Cheng ,  Cheng-Pu Chiu ,  Te-Chang Hsu ,  Chin-Yang Hsieh ,  An-Chi Liu ,  Kuan-Lin Chen ,  Yao-Jhan Wang

IPC: H01L21/8234 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/762

Abstract: A method of fabricating fins includes providing a silicon substrate. The silicon substrate is etched to form numerous fin elements. A surface of each of the fin elements is silicon. Etch residues are formed on the fin elements after the silicon substrate is etched. After that, a flush step is performed on the fin elements by flushing the surface of each of the fin elements with fluorocarbons. The etch residues on the fin elements are removed by the flush step. After the flush step, a strip step is performed on the fin elements by treating the surface of each of the fin elements with oxygen plasma.

公开(公告)号：US10109531B1

公开(公告)日：2018-10-23

申请号：US15616936

申请日：2017-06-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Te-Chang Hsu ,  An-Chi Liu ,  Nan-Yuan Huang ,  Yu-Chih Su ,  Cheng-Pu Chiu ,  Tien-Shan Hsu ,  Chih-Yi Wang ,  Chi-Hsuan Cheng

IPC: H01L21/8234 ,  H01L21/308 ,  H01L21/762

Abstract: A semiconductor structure includes a substrate, a plurality of fin shaped structures, a trench, and a first bump. The substrate has a base, and the fin shaped structures protrude from the base. The trench is recessed from the base of the substrate. The first bump is disposed within the trench and protrudes from a bottom surface of the trench. A topmost portion of the first bump is lower than the base, and a width of the first bump is larger than a width of each of the fin shaped structures.