公开(公告)号：US08866536B1

公开(公告)日：2014-10-21

申请号：US14079655

申请日：2013-11-14

Applicant: United Microelectronics Corp.

Inventor： Hsi-Wen Chen

IPC: G05F1/10 ,  G05F3/08

CPC classification number: G05F3/08 ,  G11C5/145 ,  G11C7/04 ,  G11C16/30 ,  H02M3/07

Abstract: A process monitoring circuit may be used to determine appropriate voltage for integrated circuits including a non-volatile memory. The process monitoring circuit includes a bandgap reference, a clock generator, a negative bias circuit, a temperature insensitive oscillator, a low dropout voltage regulator, a counter, a comparison circuit, and a charge. The process monitoring circuit may also include a pulse width generator. The process monitoring circuit is able to determine the process corner of which a monitored circuit belongs to and generate an output voltage according to the process corner of the monitored circuit.

Abstract translation: 可以使用过程监视电路来确定包括非易失性存储器的集成电路的适当电压。 过程监控电路包括带隙参考，时钟发生器，负偏置电路，不温度不敏感振荡器，低压差稳压器，计数器，比较电路和电荷。 过程监控电路还可以包括脉冲宽度发生器。 过程监控电路能够确定监控电路所属的过程角，并根据被监控电路的过程角产生输出电压。

公开(公告)号：US20150170718A1

公开(公告)日：2015-06-18

申请号：US14108360

申请日：2013-12-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsi-Wen Chen ,  Hsin-Pang Lu

IPC: G11C7/06 ,  G11C7/22 ,  G11C7/12

CPC classification number: G11C7/062 ,  G11C7/12 ,  G11C7/22 ,  G11C16/28 ,  G11C2207/2227

Abstract: A sense amplifier circuit may be used for read operation of a non-volatile memory. The sense amplifier circuit includes of a first pre-charge circuit, a second pre-charge circuit, a bias circuit, an enable circuit, a current mirror, a first comparator, a second comparator, a buffer and a counter. The current mirror is able to amplify a cell current of a memory cell to prevent error and shorten or maintain access time as erase count of the memory cell increases.

Abstract translation: 读出放大器电路可用于非易失性存储器的读取操作。 读出放大器电路包括第一预充电电路，第二预充电电路，偏置电路，使能电路，电流镜，第一比较器，第二比较器，缓冲器和计数器。 当前镜像能够放大存储器单元的单元电流，以防止错误，并且随着存储器单元的擦除计数增加而缩短或维持访问时间。

公开(公告)号：US20140355360A1

公开(公告)日：2014-12-04

申请号：US13906352

申请日：2013-05-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsi-Wen Chen

IPC: G11C7/08 ,  G11C7/06

CPC classification number: G11C7/08 ,  G11C7/04 ,  G11C7/065 ,  G11C7/067 ,  G11C7/14 ,  G11C11/419

Abstract: A sense amplifier includes a sensing circuit and an equalizing circuit. The sensing circuit is configured to supply one or more output signals according to one or more input signals. The equalizing circuit is configured to bring the sensing circuit to a metastable state from which the sensing circuit switches to an inverting state in response to a potential of the one or more input signals. Each transistor in the sensing circuit may switch to logic 0 or logic 1 faster and die-to-die PVT variations may be compensated, thereby providing high speed and low offset read operation.

Abstract translation: 读出放大器包括感测电路和均衡电路。 感测电路被配置为根据一个或多个输入信号提供一个或多个输出信号。 均衡电路被配置为响应于一个或多个输入信号的电位使感测电路处于亚稳态，感测电路从该电路切换到反相状态。 感测电路中的每个晶体管可以更快地切换到逻辑0或逻辑1，并且可以补偿管芯到管芯PVT变化，从而提供高速度和低偏移读取操作。

公开(公告)号：US09263134B2

公开(公告)日：2016-02-16

申请号：US14215091

申请日：2014-03-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ya-Nan Mou ,  Hsin-Pang Lu ,  Hsi-Wen Chen

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C8/08 ,  G11C8/10 ,  G11C8/14

CPC classification number: G11C16/08 ,  G11C8/08 ,  G11C8/10 ,  G11C8/14 ,  G11C16/0483 ,  G11C16/10

Abstract: A non-volatile memory cell includes a plurality of rows of memory cells, a plurality of bit lines coupled to the plurality of rows of memory cells for accessing data to the plurality of rows of memory cells, a plurality of word lines each coupled to a corresponding row of memory cells, and a decoder coupled to the plurality of word lines for enabling at least one row of memory cells of the plurality of rows of memory cells.

Abstract translation: 非易失性存储单元包括多行存储单元，耦合到多行存储单元的多个位线，用于访问到多行存储单元的数据;多个字线，每个字线与 耦合到所述多个字线的解码器，用于使所述多行存储器单元中的至少一行存储器单元能够使用。

公开(公告)号：US20150262621A1

公开(公告)日：2015-09-17

申请号：US14215091

申请日：2014-03-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ya-Nan Mou ,  Hsin-Pang Lu ,  Hsi-Wen Chen

IPC: G11C5/06 ,  G11C16/08

CPC classification number: G11C16/08 ,  G11C8/08 ,  G11C8/10 ,  G11C8/14 ,  G11C16/0483 ,  G11C16/10

Abstract: A non-volatile memory cell includes a plurality of rows of memory cells, a plurality of bit lines coupled to the plurality of rows of memory cells for accessing data to the plurality of rows of memory cells, a plurality of word lines each coupled to a corresponding row of memory cells, and a decoder coupled to the plurality of word lines for enabling at least one row of memory cells of the plurality of rows of memory cells.

Abstract translation: 非易失性存储单元包括多行存储单元，耦合到多行存储单元的多个位线，用于访问到多行存储单元的数据;多个字线，每个字线与 耦合到所述多个字线的解码器，用于使所述多行存储器单元中的至少一行存储器单元能够使用。

公开(公告)号：US09093131B2

公开(公告)日：2015-07-28

申请号：US14108360

申请日：2013-12-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsi-Wen Chen ,  Hsin-Pang Lu

IPC: G11C16/06 ,  G11C7/06 ,  G11C7/12 ,  G11C7/22

CPC classification number: G11C7/062 ,  G11C7/12 ,  G11C7/22 ,  G11C16/28 ,  G11C2207/2227

Abstract: A sense amplifier circuit may be used for read operation of a non-volatile memory. The sense amplifier circuit includes of a first pre-charge circuit, a second pre-charge circuit, a bias circuit, an enable circuit, a current mirror, a first comparator, a second comparator, a buffer and a counter. The current mirror is able to amplify a cell current of a memory cell to prevent error and shorten or maintain access time as erase count of the memory cell increases.

公开(公告)号：US20150095728A1

公开(公告)日：2015-04-02

申请号：US14040752

申请日：2013-09-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Pang Lu ,  Hsi-Wen Chen ,  Ya-Nan Mou ,  Chung-Cheng Tsai ,  Hsiao-Chieh Sung ,  Yin-Ju Hsiao

IPC: G11C29/00

CPC classification number: G11C29/04 ,  G11C29/006

Abstract: A testing method for non-volatile memory includes writing a first set of data to a set of addresses in a non-volatile memory, reading a second set of data from the set of addresses, and writing the first set of data to the set of addresses again if the first set of data and the second set of data are not identical and number of times for writing the first set of data to the set of addresses is smaller than a predetermined number.

Abstract translation: 用于非易失性存储器的测试方法包括将第一组数据写入非易失性存储器中的一组地址，从该地址集中读取第二组数据，以及将第一组数据写入到 如果第一组数据和第二组数据不相同，并且将第一组数据写入地址集合的次数小于预定数量，则再次寻址。

公开(公告)号：US08947911B1

公开(公告)日：2015-02-03

申请号：US14074478

申请日：2013-11-07

Applicant: United Microelectronics Corp.

Inventor： Hsi-Wen Chen

IPC: G11C11/00 ,  G11C11/419

CPC classification number: G11C11/419

Abstract: A bit line power implementing circuit is provided, the bit line power implementing circuit has a bit line discharge oscillator to convert the supply voltage to a pulse; a decoder coupled to the bit line discharge oscillator to decode the pulse, and providing a first pulse with a first frequency and a second pulse with a second frequency; a first and a second counters, coupled to the decoder, and receiving the first and the second pulses respectively, and outputting a signal proportional to an average and a minimum read currents respectively; a divider outputting a read current ratio of the average read current to the minimum read current; and a multiplier for multiplying the supply voltage the read current ratio to output a bit line power consumption corresponding to the supply voltage.

Abstract translation: 提供了位线功率实现电路，位线功率实现电路具有位线放电振荡器以将电源电压转换为脉冲; 耦合到所述位线放电振荡器以解码所述脉冲的解码器，以及提供具有第二频率的第一频率和第二脉冲的第一脉冲; 第一和第二计数器，耦合到解码器，并分别接收第一和第二脉冲，并分别输出与平均和最小读取电流成比例的信号; 分频器，将平均读取电流的读取电流比输出到最小读取电流; 以及乘法器，用于将电源电压乘以读电流比，以输出与电源电压相对应的位线功耗。